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On platforms where DMA devices are not in the same coherency domain as the CPU cache, it is necessary to create page table entries where the translations are marked as uncacheable. We choose to place iPXE within the low 4GB of memory (since 32-bit DMA devices are still reasonably common even on systems with 64-bit CPUs). We therefore need to cover only the low 4GB of memory with these page table entries. Update virt_to_phys() to allow for the existence of such a mapping, assuming that iPXE itself will always reside within the top 4GB of the 64-bit virtual address space (and therefore that the DMA mapping must lie somewhere below this in the negative virtual address space). Signed-off-by: Michael Brown <mcb30@ipxe.org>
iPXE README File Quick start guide: cd src make For any more detailed instructions, see http://ipxe.org