mirror of
https://github.com/ipxe/ipxe
synced 2025-12-12 14:32:49 +03:00
9b1ec3132f
On some systems, it appears to be possible for writes to the EEPROM registers to be delayed for long enough that the EEPROM's setup and hold times are violated, resulting in invalid data being read from the EEPROM. Fix by inserting a PCI read cycle immediately after writes to RTL_9346CR, to ensure that the write has completed before starting the udelay() used to time the SPI bus transitions. Reported-by: Gelip <mrgelip@gmail.com> Tested-by: Gelip <mrgelip@gmail.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
iPXE README File Quick start guide: cd src make For any more detailed instructions, see http://ipxe.org