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The RISC-V specification states that "if SATP is written with an unsupported mode, the entire write has no effect; no fields in SATP are modified". We currently rely on this specified behaviour when calculating the early UART base address: if SATP has a non-zero value then we assume that paging must be enabled. The XuanTie C910 CPU (as used in the Lichee Pi 4A) does not conform to this specified behaviour. Writing SATP with an unsupported mode will leave SATP.MODE as zero (i.e. bare physical addressing) but the write to SATP.PPN will still take effect, leaving SATP with an illegal non-zero value. Work around this misbehaviour by explicitly writing zero to SATP if we detect that the mode change has not taken effect (e.g. because the CPU does not support the requested paging mode). Signed-off-by: Michael Brown <mcb30@ipxe.org>
iPXE README File Quick start guide: cd src make For any more detailed instructions, see http://ipxe.org