mirror of
https://github.com/ipxe/ipxe
synced 2025-12-11 14:03:29 +03:00
592755eccf
Some older RTL8139 chips seem to not immediately update the RTL_CR.BUFE bit in response to a write to RTL_CAPR. This results in iPXE seeing a spurious zero-length received packet, and thereafter being out of sync with the hardware's RX ring offset. Fix by inserting an extra PCI read cycle after writing to RTL_CAPR, to give the chip time to react before we next read RTL_CR. Reported-by: Gelip <mrgelip@gmail.com> Tested-by: Gelip <mrgelip@gmail.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
iPXE README File Quick start guide: cd src make For any more detailed instructions, see http://ipxe.org