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The RISC-V "fence" instruction encoding includes bits for predecessor and successor input and output operations, separate from read and write operations. It is up to the CPU implementation to decide what counts as I/O space rather than memory space for the purposes of this instruction. Since we do not expect fencing to be performance-critical, keep everything as simple and reliable as possible by using the unadorned "fence" instruction (equivalent to "fence iorw, iorw"). Add a memory clobber to ensure that the compiler does not reorder the barrier. (The volatile qualifier seems to already prevent reordering in practice, but this is not guaranteed according to the compiler documentation.) Signed-off-by: Michael Brown <mcb30@ipxe.org>
iPXE README File Quick start guide: cd src make For any more detailed instructions, see http://ipxe.org