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iPXE drivers have been written with the implicit assumption that MMIO writes are allowed to be posted but that an MMIO register read or write after another MMIO register write will always observe the effects of the first write. For example: after having written a byte to the transmit holding register (THR) of a 16550 UART, it is expected that any subsequent read of the line status register (LSR) will observe a value consistent with the occurrence of the write. RISC-V does not seem to provide any ordering guarantees between accesses to different registers within the same MMIO device. Add fences as part of the MMIO accessors to provide the assumed guarantees. Use "fence io, io" before each MMIO read or write to enforce full serialisation of MMIO accesses with respect to each other. This is almost certainly more conservative than is strictly necessary. Signed-off-by: Michael Brown <mcb30@ipxe.org>
iPXE README File Quick start guide: cd src make For any more detailed instructions, see http://ipxe.org