[dwuart] Read input clock frequency from the device tree

The 16550 design includes a programmable 16-bit clock divider for an
arbitrary input clock, requiring knowledge of the input clock
frequency in order to calculate the divider value for a given baud
rate.  The 16550 UARTs in an x86 PC will always have a 1.8432 MHz
input clock.  Non-x86 systems may have other input clock frequencies.

Define the input clock frequency as a property of a 16550 UART, and
read the value from the device tree "clock-frequency" property.

Signed-off-by: Michael Brown <mcb30@ipxe.org>

src/include/ipxe/ns16550.h

@@ -73,19 +73,24 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
 /** Divisor latch (most significant byte) */
 #define NS16550_DLM 0x01
 
-/** Maximum baud rate */
-#define NS16550_MAX_BAUD 115200
-
 /** A 16550-compatible UART */
 struct ns16550_uart {
 	/** Register base address */
 	void *base;
 	/** Register shift */
 	unsigned int shift;
+	/** Input clock frequency */
+	unsigned int clock;
 	/** Baud rate divisor */
 	uint16_t divisor;
 };
 
+/** Post-division clock cycles per data bit */
+#define NS16550_CLK_BIT 16
+
+/** Default input clock rate (1.8432 MHz) */
+#define NS16550_CLK_DEFAULT 1843200
+
 #include <bits/ns16550.h>
 
 /** Dummy COM1 UART for non-x86 platforms