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[riscv] Add fences around early UART writes

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Add a fence between the write to the UART transmit register and the
subsequent read from the transmit status register, to ensure that the
status correctly reflects the occurrence of the write.

Signed-off-by: Michael Brown <mcb30@ipxe.org>
This commit is contained in:
Michael Brown
2025-06-02 08:36:22 +01:00
parent 88cffd75a9
commit 7df005c4c6
1 changed files with 2 additions and 0 deletions
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2
src/arch/riscv/prefix/libprefix.S
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@@ -204,6 +204,7 @@ early_uart_reg_base_64_done_\@:
.macro print_char_uart_8250
early_uart_reg_base a7
sb a0, EARLY_UART_8250_TX(a7)
fence
early_uart_8250_wait_\@:
lbu a1, EARLY_UART_8250_LSR(a7)
andi a1, a1, EARLY_UART_8250_LSR_THRE
@@ -236,6 +237,7 @@ early_uart_8250_wait_\@:
.macro print_char_uart_sifive
early_uart_reg_base a7
sw a0, EARLY_UART_SIFIVE_TXFIFO(a7)
fence
early_uart_sifive_wait_\@:
lw a1, EARLY_UART_SIFIVE_TXFIFO(a7)
bltz a1, early_uart_sifive_wait_\@