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https://github.com/ipxe/ipxe
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[riscv] Add support for enabling 32-bit paging
Add code to construct a 32-bit page table to map the whole of the 32-bit address space with a fixed offset selected to map iPXE itself at its link-time address, and to return with paging enabled and the program counter updated to a virtual address. Signed-off-by: Michael Brown <mcb30@ipxe.org>
This commit is contained in:
Michael Brown
@@ -138,6 +138,9 @@ reloc_base:
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/** Number of page table entries */
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#define PTE_COUNT ( PAGE_SIZE / PTE_SIZE )
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/** Number of bits in a virtual or physical page number */
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#define VPPN_SHIFT ( PAGE_SHIFT - PTE_SIZE_LOG2 )
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/* Page table entry flags */
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#define PTE_V 0x00000001 /**< Page table entry is valid */
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#define PTE_R 0x00000002 /**< Page is readable */
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@@ -146,20 +149,27 @@ reloc_base:
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#define PTE_A 0x00000040 /**< Page has been accessed */
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#define PTE_D 0x00000080 /**< Page is dirty */
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#define PTE_PPN4_LSB 46 /**< PPN[4] LSB (Sv57) */
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#define PTE_PPN3_LSB 37 /**< PPN[3] LSB (Sv57 and Sv48) */
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#define PTE_PPN2_LSB 28 /**< PPN[2] LSB (all levels) */
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#define PTE_PPN1_LSB 19 /**< PPN[1] LSB (all levels) */
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#define PTE_PPN0_LSB 10 /**< PPN[0] LSB (all levels) */
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/* Page table entry flags for our leaf pages */
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#define PTE_LEAF ( PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V )
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/** Physical page number LSB in PTE */
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#define PTE_PPN_LSB(x) ( 10 + (x) * VPPN_SHIFT )
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#define PTE_PPN4_LSB PTE_PPN_LSB(4) /**< PPN[4] LSB (Sv57) */
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#define PTE_PPN3_LSB PTE_PPN_LSB(3) /**< PPN[3] LSB (Sv57 & Sv48) */
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#define PTE_PPN2_LSB PTE_PPN_LSB(2) /**< PPN[2] LSB (Sv57, Sv48, & Sv39) */
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#define PTE_PPN1_LSB PTE_PPN_LSB(1) /**< PPN[1] LSB (all levels) */
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#define PTE_PPN0_LSB PTE_PPN_LSB(0) /**< PPN[0] LSB (all levels) */
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/** Page table entry physical page address shift */
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#define PTE_PPN_SHIFT ( PAGE_SHIFT - PTE_PPN0_LSB )
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#define VPN4_LSB 48 /**< VPN[4] LSB (Sv57) */
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#define VPN3_LSB 39 /**< VPN[3] LSB (Sv57 and Sv48) */
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#define VPN2_LSB 30 /**< VPN[2] LSB (all levels) */
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#define VPN1_LSB 21 /**< VPN[1] LSB (all levels) */
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#define VPN0_LSB 12 /**< VPN[0] LSB (all levels) */
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/** Virtual page number LSB */
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#define VPN_LSB(x) ( PAGE_SHIFT + (x) * VPPN_SHIFT )
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#define VPN4_LSB VPN_LSB(4) /**< VPN[4] LSB (Sv57) */
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#define VPN3_LSB VPN_LSB(3) /**< VPN[3] LSB (Sv57 & Sv48) */
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#define VPN2_LSB VPN_LSB(2) /**< VPN[2] LSB (Sv57, Sv48, & Sv39) */
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#define VPN1_LSB VPN_LSB(1) /**< VPN[1] LSB (all levels) */
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#define VPN0_LSB VPN_LSB(0) /**< VPN[0] LSB (all levels) */
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/* Paging modes */
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#define SATP_MODE_SV57 10 /**< Five-level paging (Sv57) */
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@@ -177,6 +187,12 @@ reloc_base:
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.globl enable_paging
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.equ enable_paging, _C2 ( enable_paging_, __riscv_xlen )
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/* Link-time address of _prefix */
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.section ".rodata.prefix_virt", "a", @progbits
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prefix_virt:
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.dword _prefix
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.size prefix_virt, . - prefix_virt
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/*****************************************************************************
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*
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* Enable 64-bit paging
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@@ -285,7 +301,7 @@ enable_paging_64_loop:
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/* Construct PTE[0-255] for identity map */
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mv a3, a2
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li t0, ( PTE_COUNT / 2 )
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li t1, ( PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V )
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li t1, PTE_LEAF
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1: STOREN t1, (a3)
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addi a3, a3, PTE_SIZE
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add t1, t1, a4
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@@ -323,7 +339,7 @@ enable_paging_64_loop:
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/* Construct PTE[x-y] for iPXE virtual address map */
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la t0, _prefix
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srli t0, t0, PTE_PPN_SHIFT
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ori t0, t0, ( PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V )
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ori t0, t0, PTE_LEAF
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la t1, _ebss
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srli t1, t1, PTE_PPN_SHIFT
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1: STOREN t0, (a3)
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@@ -359,8 +375,116 @@ enable_paging_64_done:
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ret
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.size enable_paging_64, . - enable_paging_64
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/* Link-time address of _prefix */
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.section ".rodata.prefix_virt", "a", @progbits
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prefix_virt:
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.dword _prefix
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.size prefix_virt, . - prefix_virt
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/*****************************************************************************
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*
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* Enable 32-bit paging
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*
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*****************************************************************************
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*
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* Construct a 32-bit page table to map the whole of the 32-bit
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* address space with a fixed offset selected to map iPXE itself at
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* its link-time address (which must be 4MB-aligned).
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*
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* This function must be called with flat physical addressing. It
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* does not require a valid stack pointer.
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*
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* Parameters:
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*
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* a0 - Page table to fill in (4kB, must be aligned to a 4kB boundary)
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*
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* Returns:
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*
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* a0 - Selected paging mode (0=no paging)
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* pc - Updated to a virtual address if paging enabled
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*
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* A 4kB 32-bit page table contains 1024 4-byte PTEs. We choose to
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* use these to produce a circular map of the 32-bit address space
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* using 4MB "megapages", with a fixed offset to align the virtual and
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* link-time addresses.
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*
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* To handle the transition from physical to virtual addresses, we
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* temporarily adjust the PTE covering the current program counter to
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* be a direct physical map (so that the program counter remains valid
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* at the moment when paging is enabled), then jump to a virtual
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* address, then restore the temporarily modified PTE.
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*/
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.equ enable_paging_32_xalign, 16
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.section ".prefix.enable_paging_32", "ax", @progbits
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enable_paging_32:
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/* Register usage:
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*
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* a0 - return value (enabled paging level)
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* a1 - virtual address offset
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* a2 - page table base address
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* a3 - PTE pointer
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* a4 - saved content of temporarily modified PTE
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*/
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mv a2, a0
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/* Calculate virtual address offset */
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la t0, prefix_virt
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LOADN t0, (t0)
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la t1, _prefix
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sub a1, t1, t0
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/* Construct PTEs for circular map */
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mv a3, a2
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li t0, PTE_COUNT
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mv t1, a1
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ori t1, t1, ( PTE_LEAF << PTE_PPN_SHIFT )
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li t2, ( 1 << ( PTE_PPN1_LSB + PTE_PPN_SHIFT ) )
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1: srli t3, t1, PTE_PPN_SHIFT
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STOREN t3, (a3)
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addi a3, a3, PTE_SIZE
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add t1, t1, t2
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addi t0, t0, -1
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bgtz t0, 1b
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/* Temporarily modify PTE for transition code to be an identity map */
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la t0, enable_paging_32_xstart
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srli t0, t0, VPN1_LSB
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slli t1, t0, PTE_SIZE_LOG2
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add a3, a2, t1
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LOADN a4, (a3)
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slli t0, t0, PTE_PPN1_LSB
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ori t0, t0, PTE_LEAF
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STOREN t0, (a3)
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/* Attempt to enable paging, and read back active paging level */
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la t0, 1f
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sub t0, t0, a1
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li t1, ( SATP_MODE_SV32 << SATP_MODE_SHIFT )
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srli t2, a2, PAGE_SHIFT
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or t1, t1, t2
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.balign enable_paging_32_xalign
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/* Start of transition code */
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enable_paging_32_xstart:
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csrrw zero, satp, t1
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sfence.vma
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csrrw a0, satp, t1
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beqz a0, enable_paging_32_done
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jr t0
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1: /* End of transition code */
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.equ enable_paging_32_xlen, . - enable_paging_32_xstart
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li a0, 1
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/* Adjust PTE pointer to a virtual address */
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sub a3, a3, a1
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/* Restore temporarily modified PTE */
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STOREN a4, (a3)
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sfence.vma
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/* Adjust return address */
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sub ra, ra, a1
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enable_paging_32_done:
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/* Return, with or without paging enabled */
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ret
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.size enable_paging_32, . - enable_paging_32
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/* Ensure that transition code did not cross an alignment boundary */
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.section ".bss.enable_paging_32_xcheck", "aw", @nobits
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.org . + enable_paging_32_xalign - enable_paging_32_xlen
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