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[riscv] Ensure coherent DMA allocations do not cross cacheline boundaries

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Signed-off-by: Michael Brown <mcb30@ipxe.org>
This commit is contained in:
Michael Brown
2025-07-11 13:50:41 +01:00
parent d539a420df
commit 434462a93e
1 changed files with 15 additions and 0 deletions
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15
src/arch/riscv/core/riscv_dma.c
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@@ -34,6 +34,13 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
*
*/
/** Minimum alignment for coherent DMA allocations
*
* We set this sufficiently high to ensure that we do not end up with
* both cached and uncached uses in the same cacheline.
*/
#define RISCV_DMA_ALIGN 256
/**
* Map buffer for DMA
*
@@ -111,6 +118,11 @@ static void * riscv_dma_alloc ( struct dma_device *dma,
void *addr;
void *caddr;
/* Round up length and alignment */
len = ( ( len + RISCV_DMA_ALIGN - 1 ) & ~( RISCV_DMA_ALIGN - 1 ) );
if ( align < RISCV_DMA_ALIGN )
align = RISCV_DMA_ALIGN;
/* Allocate from heap */
addr = malloc_phys ( len, align );
if ( ! addr )
@@ -153,6 +165,9 @@ static void riscv_dma_free ( struct dma_mapping *map,
/* Sanity check */
assert ( virt_to_phys ( addr ) == virt_to_phys ( map->token ) );
/* Round up length to match allocation */
len = ( ( len + RISCV_DMA_ALIGN - 1 ) & ~( RISCV_DMA_ALIGN - 1 ) );
/* Free original allocation */
free_phys ( map->token, len );