[riscv] Use 1GB pages for I/O device mappings

All 64-bit paging schemes support at least 1GB "gigapages".  Use these
to map I/O devices instead of 2MB "megapages".  This reduces the
number of consumed page table entries, increases the visual similarity
of I/O remapped addresses to the underlying physical addresses, and
opens up the possibility of reusing the code to create the coherent
DMA map of the 32-bit address space.

Signed-off-by: Michael Brown <mcb30@ipxe.org>
This commit is contained in:
Michael Brown
2025-07-11 11:30:57 +01:00
parent c2cdc1d31e
commit 0611ddbd12

View File

@@ -35,10 +35,10 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
* With the 64-bit paging schemes (Sv39, Sv48, and Sv57) we choose to
* identity-map as much as possible of the physical address space via
* PTEs 0-255, and place a recursive page table entry in PTE 511 which
* allows PTEs 256-510 to be used to map 2MB "megapages" within the
* top 512MB of the 64-bit address space. At least one of these 2MB
* PTEs will already be in use to map iPXE itself. The remaining PTEs
* may be used to map I/O devices.
* allows PTEs 256-510 to be used to map 1GB "gigapages" within the
* top 256GB of the 64-bit address space. At least one of these PTEs
* will already be in use to map iPXE itself. The remaining PTEs may
* be used to map I/O devices.
*/
/** A page table */
@@ -75,17 +75,17 @@ extern struct page_table page_table;
/** I/O page size
*
* We choose to use 2MB "megapages", since these are supported by all
* We choose to use 1GB "gigapages", since these are supported by all
* paging levels.
*/
#define IO_PAGE_SIZE 0x200000UL
#define IO_PAGE_SIZE 0x40000000UL
/** I/O page base address
*
* The recursive page table entry maps the high 1024MB of the 64-bit
* address space as 2MB "megapages".
* The recursive page table entry maps the high 512GB of the 64-bit
* address space as 1GB "gigapages".
*/
#define IO_BASE ( ( void * ) ( intptr_t ) ( -1024 * 1024 * 1024 ) )
#define IO_BASE ( ( void * ) ( intptr_t ) ( -1ULL << 39 ) )
/**
* Map pages for I/O