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[riscv] Use 1GB pages for I/O device mappings
All 64-bit paging schemes support at least 1GB "gigapages". Use these to map I/O devices instead of 2MB "megapages". This reduces the number of consumed page table entries, increases the visual similarity of I/O remapped addresses to the underlying physical addresses, and opens up the possibility of reusing the code to create the coherent DMA map of the 32-bit address space. Signed-off-by: Michael Brown <mcb30@ipxe.org>
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@@ -35,10 +35,10 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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* With the 64-bit paging schemes (Sv39, Sv48, and Sv57) we choose to
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* identity-map as much as possible of the physical address space via
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* PTEs 0-255, and place a recursive page table entry in PTE 511 which
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* allows PTEs 256-510 to be used to map 2MB "megapages" within the
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* top 512MB of the 64-bit address space. At least one of these 2MB
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* PTEs will already be in use to map iPXE itself. The remaining PTEs
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* may be used to map I/O devices.
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* allows PTEs 256-510 to be used to map 1GB "gigapages" within the
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* top 256GB of the 64-bit address space. At least one of these PTEs
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* will already be in use to map iPXE itself. The remaining PTEs may
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* be used to map I/O devices.
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*/
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/** A page table */
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@@ -75,17 +75,17 @@ extern struct page_table page_table;
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/** I/O page size
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*
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* We choose to use 2MB "megapages", since these are supported by all
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* We choose to use 1GB "gigapages", since these are supported by all
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* paging levels.
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*/
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#define IO_PAGE_SIZE 0x200000UL
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#define IO_PAGE_SIZE 0x40000000UL
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/** I/O page base address
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*
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* The recursive page table entry maps the high 1024MB of the 64-bit
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* address space as 2MB "megapages".
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* The recursive page table entry maps the high 512GB of the 64-bit
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* address space as 1GB "gigapages".
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*/
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#define IO_BASE ( ( void * ) ( intptr_t ) ( -1024 * 1024 * 1024 ) )
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#define IO_BASE ( ( void * ) ( intptr_t ) ( -1ULL << 39 ) )
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/**
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* Map pages for I/O
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