mirror of
https://github.com/ipxe/ipxe
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2ae5355321
The behaviour of PCI devices across a function-level reset seems to be inconsistent in practice: some devices will preserve PCI BARs, some will not. Fix the behaviour of FLR on devices that do not preserve PCI BARs by backing up and restoring PCI configuration space across the reset. Preserve only the standard portion of the configuration space, since there may be registers with unexpected side effects in the remaining non-standardised space. Signed-off-by: Michael Brown <mcb30@ipxe.org>
142 lines
4.0 KiB
C
142 lines
4.0 KiB
C
FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#include <stdint.h>
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#include <ipxe/timer.h>
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#include <ipxe/pci.h>
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#include <ipxe/pcibackup.h>
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static int pci_find_capability_common ( struct pci_device *pci,
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uint8_t pos, int cap ) {
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uint8_t id;
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int ttl = 48;
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while ( ttl-- && pos >= 0x40 ) {
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pos &= ~3;
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pci_read_config_byte ( pci, pos + PCI_CAP_ID, &id );
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DBG ( "PCI Capability: %d\n", id );
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if ( id == 0xff )
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break;
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if ( id == cap )
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return pos;
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pci_read_config_byte ( pci, pos + PCI_CAP_NEXT, &pos );
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}
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return 0;
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}
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/**
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* Look for a PCI capability
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*
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* @v pci PCI device to query
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* @v cap Capability code
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* @ret address Address of capability, or 0 if not found
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*
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* Determine whether or not a device supports a given PCI capability.
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* Returns the address of the requested capability structure within
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* the device's PCI configuration space, or 0 if the device does not
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* support it.
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*/
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int pci_find_capability ( struct pci_device *pci, int cap ) {
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uint16_t status;
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uint8_t pos;
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uint8_t hdr_type;
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pci_read_config_word ( pci, PCI_STATUS, &status );
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if ( ! ( status & PCI_STATUS_CAP_LIST ) )
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return 0;
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pci_read_config_byte ( pci, PCI_HEADER_TYPE, &hdr_type );
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switch ( hdr_type & PCI_HEADER_TYPE_MASK ) {
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case PCI_HEADER_TYPE_NORMAL:
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case PCI_HEADER_TYPE_BRIDGE:
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default:
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pci_read_config_byte ( pci, PCI_CAPABILITY_LIST, &pos );
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break;
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case PCI_HEADER_TYPE_CARDBUS:
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pci_read_config_byte ( pci, PCI_CB_CAPABILITY_LIST, &pos );
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break;
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}
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return pci_find_capability_common ( pci, pos, cap );
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}
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/**
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* Look for another PCI capability
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*
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* @v pci PCI device to query
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* @v pos Address of the current capability
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* @v cap Capability code
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* @ret address Address of capability, or 0 if not found
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*
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* Determine whether or not a device supports a given PCI capability
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* starting the search at a given address within the device's PCI
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* configuration space. Returns the address of the next capability
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* structure within the device's PCI configuration space, or 0 if the
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* device does not support another such capability.
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*/
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int pci_find_next_capability ( struct pci_device *pci, int pos, int cap ) {
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uint8_t new_pos;
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pci_read_config_byte ( pci, pos + PCI_CAP_NEXT, &new_pos );
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return pci_find_capability_common ( pci, new_pos, cap );
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}
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/**
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* Find the size of a PCI BAR
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*
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* @v pci PCI device
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* @v reg PCI register number
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* @ret size BAR size
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*
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* It should not be necessary for any Etherboot code to call this
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* function.
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*/
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unsigned long pci_bar_size ( struct pci_device *pci, unsigned int reg ) {
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uint16_t cmd;
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uint32_t start, size;
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/* Save the original command register */
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pci_read_config_word ( pci, PCI_COMMAND, &cmd );
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/* Save the original bar */
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pci_read_config_dword ( pci, reg, &start );
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/* Compute which bits can be set */
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pci_write_config_dword ( pci, reg, ~0 );
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pci_read_config_dword ( pci, reg, &size );
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/* Restore the original size */
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pci_write_config_dword ( pci, reg, start );
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/* Find the significant bits */
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/* Restore the original command register. This reenables decoding. */
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pci_write_config_word ( pci, PCI_COMMAND, cmd );
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if ( start & PCI_BASE_ADDRESS_SPACE_IO ) {
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size &= ~PCI_BASE_ADDRESS_IO_MASK;
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} else {
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size &= ~PCI_BASE_ADDRESS_MEM_MASK;
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}
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/* Find the lowest bit set */
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size = size & ~( size - 1 );
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return size;
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}
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/**
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* Perform PCI Express function-level reset (FLR)
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*
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* @v pci PCI device
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* @v exp PCI Express Capability address
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*/
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void pci_reset ( struct pci_device *pci, unsigned int exp ) {
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struct pci_config_backup backup;
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uint16_t control;
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/* Back up configuration space */
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pci_backup ( pci, &backup, PCI_CONFIG_BACKUP_STANDARD, NULL );
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/* Perform a PCIe function-level reset */
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pci_read_config_word ( pci, ( exp + PCI_EXP_DEVCTL ), &control );
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control |= PCI_EXP_DEVCTL_FLR;
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pci_write_config_word ( pci, ( exp + PCI_EXP_DEVCTL ), control );
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/* Allow time for reset to complete */
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mdelay ( PCI_EXP_FLR_DELAY_MS );
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/* Restore configuration */
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pci_restore ( pci, &backup, PCI_CONFIG_BACKUP_STANDARD, NULL );
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}
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