Michael Brown dad2060260 [riscv] Allow for a non-zero link-time address ...

Using paging (rather than relocation records) will be easier on 64-bit
RISC-V if we place iPXE within the negative (kernel) virtual address
space.

Allow the link-time address to be non-zero and to vary between 32-bit
and 64-bit builds.  Choose addresses that are expected to be amenable
to the use of paging.

There is no particular need to use a non-zero address in the 32-bit
builds, but doing so allows us to validate that the relocation code is
handling this case correctly.

Signed-off-by: Michael Brown <mcb30@ipxe.org>

2025-05-01 14:49:53 +01:00

..

core

[riscv] Add support for the RISC-V CPU architecture

2024-09-15 22:34:10 +01:00

include

[sbi] Add support for running as a RISC-V SBI payload

2024-10-28 19:20:50 +00:00

Makefile

[riscv] Add support for the RISC-V CPU architecture

2024-09-15 22:34:10 +01:00

Makefile.efi

[efi] Remove redundant EFI_BOOT_FILE definitions

2024-09-16 11:04:52 +01:00

Makefile.linux

[riscv] Add support for the RISC-V CPU architecture

2024-09-15 22:34:10 +01:00

Makefile.sbi

[riscv] Allow for a non-zero link-time address

2025-05-01 14:49:53 +01:00