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https://github.com/ipxe/ipxe
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c44a193d0d
Add FILE_LICENCE declarations to almost all files that make up the various standard builds of gPXE.
195 lines
7.5 KiB
C
195 lines
7.5 KiB
C
#ifndef _PHANTOM_H
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#define _PHANTOM_H
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/*
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* Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
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* Copyright (C) 2008 NetXen, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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FILE_LICENCE ( GPL2_OR_LATER );
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/**
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* @file
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*
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* NetXen Phantom NICs
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*
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*/
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#include <stdint.h>
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/* Drag in hardware definitions */
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#include "nx_bitops.h"
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#include "phantom_hw.h"
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struct phantom_rds { NX_PSEUDO_BIT_STRUCT ( struct phantom_rds_pb ) };
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struct phantom_sds { NX_PSEUDO_BIT_STRUCT ( struct phantom_sds_pb ) };
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union phantom_cds { NX_PSEUDO_BIT_STRUCT ( union phantom_cds_pb ) };
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/* Drag in firmware interface definitions */
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typedef uint8_t U8;
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typedef uint16_t U16;
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typedef uint32_t U32;
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typedef uint64_t U64;
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typedef uint32_t nx_rcode_t;
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#define NXHAL_VERSION 1
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#include "nxhal_nic_interface.h"
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/** DMA buffer alignment */
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#define UNM_DMA_BUFFER_ALIGN 16
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/** Mark structure as DMA-aligned */
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#define __unm_dma_aligned __attribute__ (( aligned ( UNM_DMA_BUFFER_ALIGN ) ))
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/******************************************************************************
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*
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* Register definitions
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*
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*/
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#define UNM_128M_CRB_WINDOW 0x6110210UL
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#define UNM_32M_CRB_WINDOW 0x0110210UL
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#define UNM_2M_CRB_WINDOW 0x0130060UL
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/**
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* Phantom register blocks
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*
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* The upper address bits vary between cards. We define an abstract
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* address space in which the upper 8 bits of the 32-bit register
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* address encode the register block. This gets translated to a bus
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* address by the phantom_crb_access_xxx() methods.
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*/
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enum unm_reg_blocks {
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UNM_CRB_BLK_PCIE = 0x01,
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UNM_CRB_BLK_CAM = 0x22,
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UNM_CRB_BLK_ROMUSB = 0x33,
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UNM_CRB_BLK_TEST = 0x02,
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UNM_CRB_BLK_PEG_0 = 0x11,
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UNM_CRB_BLK_PEG_1 = 0x12,
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UNM_CRB_BLK_PEG_2 = 0x13,
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UNM_CRB_BLK_PEG_3 = 0x14,
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UNM_CRB_BLK_PEG_4 = 0x0f,
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};
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#define UNM_CRB_BASE(blk) ( (blk) << 20 )
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#define UNM_CRB_BLK(reg) ( (reg) >> 20 )
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#define UNM_CRB_OFFSET(reg) ( (reg) & 0x000fffff )
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#define UNM_CRB_PCIE UNM_CRB_BASE ( UNM_CRB_BLK_PCIE )
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#define UNM_PCIE_SEM2_LOCK ( UNM_CRB_PCIE + 0x1c010 )
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#define UNM_PCIE_SEM2_UNLOCK ( UNM_CRB_PCIE + 0x1c014 )
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#define UNM_CRB_CAM UNM_CRB_BASE ( UNM_CRB_BLK_CAM )
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#define UNM_CAM_RAM ( UNM_CRB_CAM + 0x02000 )
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#define UNM_CAM_RAM_PORT_MODE ( UNM_CAM_RAM + 0x00024 )
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#define UNM_CAM_RAM_PORT_MODE_AUTO_NEG 4
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#define UNM_CAM_RAM_PORT_MODE_AUTO_NEG_1G 5
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#define UNM_CAM_RAM_DMESG_HEAD(n) ( UNM_CAM_RAM + 0x00030 + (n) * 0x10 )
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#define UNM_CAM_RAM_DMESG_LEN(n) ( UNM_CAM_RAM + 0x00034 + (n) * 0x10 )
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#define UNM_CAM_RAM_DMESG_TAIL(n) ( UNM_CAM_RAM + 0x00038 + (n) * 0x10 )
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#define UNM_CAM_RAM_DMESG_SIG(n) ( UNM_CAM_RAM + 0x0003c + (n) * 0x10 )
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#define UNM_CAM_RAM_DMESG_SIG_MAGIC 0xcafebabeUL
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#define UNM_CAM_RAM_NUM_DMESG_BUFFERS 5
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#define UNM_CAM_RAM_CLP_COMMAND ( UNM_CAM_RAM + 0x000c0 )
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#define UNM_CAM_RAM_CLP_COMMAND_LAST 0x00000080UL
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#define UNM_CAM_RAM_CLP_DATA_LO ( UNM_CAM_RAM + 0x000c4 )
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#define UNM_CAM_RAM_CLP_DATA_HI ( UNM_CAM_RAM + 0x000c8 )
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#define UNM_CAM_RAM_CLP_STATUS ( UNM_CAM_RAM + 0x000cc )
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#define UNM_CAM_RAM_CLP_STATUS_START 0x00000001UL
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#define UNM_CAM_RAM_CLP_STATUS_DONE 0x00000002UL
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#define UNM_CAM_RAM_CLP_STATUS_ERROR 0x0000ff00UL
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#define UNM_CAM_RAM_CLP_STATUS_UNINITIALISED 0xffffffffUL
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#define UNM_CAM_RAM_BOOT_ENABLE ( UNM_CAM_RAM + 0x000fc )
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#define UNM_CAM_RAM_WOL_PORT_MODE ( UNM_CAM_RAM + 0x00198 )
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#define UNM_CAM_RAM_MAC_ADDRS ( UNM_CAM_RAM + 0x001c0 )
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#define UNM_CAM_RAM_COLD_BOOT ( UNM_CAM_RAM + 0x001fc )
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#define UNM_CAM_RAM_COLD_BOOT_MAGIC 0x55555555UL
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#define UNM_NIC_REG ( UNM_CRB_CAM + 0x02200 )
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#define UNM_NIC_REG_NX_CDRP ( UNM_NIC_REG + 0x00018 )
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#define UNM_NIC_REG_NX_ARG1 ( UNM_NIC_REG + 0x0001c )
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#define UNM_NIC_REG_NX_ARG2 ( UNM_NIC_REG + 0x00020 )
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#define UNM_NIC_REG_NX_ARG3 ( UNM_NIC_REG + 0x00024 )
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#define UNM_NIC_REG_NX_SIGN ( UNM_NIC_REG + 0x00028 )
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#define UNM_NIC_REG_DUMMY_BUF_ADDR_HI ( UNM_NIC_REG + 0x0003c )
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#define UNM_NIC_REG_DUMMY_BUF_ADDR_LO ( UNM_NIC_REG + 0x00040 )
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#define UNM_NIC_REG_CMDPEG_STATE ( UNM_NIC_REG + 0x00050 )
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#define UNM_NIC_REG_CMDPEG_STATE_INITIALIZED 0xff01
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#define UNM_NIC_REG_CMDPEG_STATE_INITIALIZE_ACK 0xf00f
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#define UNM_NIC_REG_DUMMY_BUF ( UNM_NIC_REG + 0x000fc )
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#define UNM_NIC_REG_DUMMY_BUF_INIT 0
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#define UNM_NIC_REG_XG_STATE_P3 ( UNM_NIC_REG + 0x00098 )
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#define UNM_NIC_REG_XG_STATE_P3_LINK( port, state_p3 ) \
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( ( (state_p3) >> ( (port) * 4 ) ) & 0x0f )
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#define UNM_NIC_REG_XG_STATE_P3_LINK_UP 0x01
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#define UNM_NIC_REG_XG_STATE_P3_LINK_DOWN 0x02
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#define UNM_NIC_REG_RCVPEG_STATE ( UNM_NIC_REG + 0x0013c )
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#define UNM_NIC_REG_RCVPEG_STATE_INITIALIZED 0xff01
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#define UNM_NIC_REG_SW_INT_MASK_0 ( UNM_NIC_REG + 0x001d8 )
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#define UNM_NIC_REG_SW_INT_MASK_1 ( UNM_NIC_REG + 0x001e0 )
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#define UNM_NIC_REG_SW_INT_MASK_2 ( UNM_NIC_REG + 0x001e4 )
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#define UNM_NIC_REG_SW_INT_MASK_3 ( UNM_NIC_REG + 0x001e8 )
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#define UNM_CRB_ROMUSB UNM_CRB_BASE ( UNM_CRB_BLK_ROMUSB )
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#define UNM_ROMUSB_GLB ( UNM_CRB_ROMUSB + 0x00000 )
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#define UNM_ROMUSB_GLB_STATUS ( UNM_ROMUSB_GLB + 0x00004 )
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#define UNM_ROMUSB_GLB_STATUS_ROM_DONE ( 1 << 1 )
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#define UNM_ROMUSB_GLB_SW_RESET ( UNM_ROMUSB_GLB + 0x00008 )
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#define UNM_ROMUSB_GLB_SW_RESET_MAGIC 0x0080000fUL
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#define UNM_ROMUSB_GLB_PEGTUNE_DONE ( UNM_ROMUSB_GLB + 0x0005c )
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#define UNM_ROMUSB_GLB_PEGTUNE_DONE_MAGIC 0x31
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#define UNM_ROMUSB_ROM ( UNM_CRB_ROMUSB + 0x10000 )
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#define UNM_ROMUSB_ROM_INSTR_OPCODE ( UNM_ROMUSB_ROM + 0x00004 )
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#define UNM_ROMUSB_ROM_ADDRESS ( UNM_ROMUSB_ROM + 0x00008 )
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#define UNM_ROMUSB_ROM_WDATA ( UNM_ROMUSB_ROM + 0x0000c )
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#define UNM_ROMUSB_ROM_ABYTE_CNT ( UNM_ROMUSB_ROM + 0x00010 )
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#define UNM_ROMUSB_ROM_DUMMY_BYTE_CNT ( UNM_ROMUSB_ROM + 0x00014 )
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#define UNM_ROMUSB_ROM_RDATA ( UNM_ROMUSB_ROM + 0x00018 )
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#define UNM_CRB_TEST UNM_CRB_BASE ( UNM_CRB_BLK_TEST )
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#define UNM_TEST_CONTROL ( UNM_CRB_TEST + 0x00090 )
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#define UNM_TEST_CONTROL_START 0x01
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#define UNM_TEST_CONTROL_ENABLE 0x02
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#define UNM_TEST_CONTROL_BUSY 0x08
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#define UNM_TEST_ADDR_LO ( UNM_CRB_TEST + 0x00094 )
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#define UNM_TEST_ADDR_HI ( UNM_CRB_TEST + 0x00098 )
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#define UNM_TEST_RDDATA_LO ( UNM_CRB_TEST + 0x000a8 )
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#define UNM_TEST_RDDATA_HI ( UNM_CRB_TEST + 0x000ac )
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#define UNM_CRB_PEG_0 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_0 )
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#define UNM_PEG_0_HALT_STATUS ( UNM_CRB_PEG_0 + 0x00030 )
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#define UNM_PEG_0_HALT ( UNM_CRB_PEG_0 + 0x0003c )
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#define UNM_CRB_PEG_1 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_1 )
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#define UNM_PEG_1_HALT_STATUS ( UNM_CRB_PEG_1 + 0x00030 )
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#define UNM_PEG_1_HALT ( UNM_CRB_PEG_1 + 0x0003c )
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#define UNM_CRB_PEG_2 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_2 )
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#define UNM_PEG_2_HALT_STATUS ( UNM_CRB_PEG_2 + 0x00030 )
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#define UNM_PEG_2_HALT ( UNM_CRB_PEG_2 + 0x0003c )
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#define UNM_CRB_PEG_3 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_3 )
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#define UNM_PEG_3_HALT_STATUS ( UNM_CRB_PEG_3 + 0x00030 )
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#define UNM_PEG_3_HALT ( UNM_CRB_PEG_3 + 0x0003c )
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#define UNM_CRB_PEG_4 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_4 )
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#define UNM_PEG_4_HALT_STATUS ( UNM_CRB_PEG_4 + 0x00030 )
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#define UNM_PEG_4_HALT ( UNM_CRB_PEG_4 + 0x0003c )
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#endif /* _PHANTOM_H */
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