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https://github.com/ipxe/ipxe
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3fe683ebab
On devices with no EEPROM or OTP, the MAC_CR register defaults to not using automatic link speed detection, with the result that no packets are successfully sent or received. Fix by always enabling automatic speed and duplex detection, since iPXE provides no mechanism for manual configuration of either link speed or duplex. Signed-off-by: Michael Brown <mcb30@ipxe.org>
104 lines
3.2 KiB
C
104 lines
3.2 KiB
C
#ifndef _LAN78XX_H
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#define _LAN78XX_H
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/** @file
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*
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* Microchip LAN78xx USB Ethernet driver
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*
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*/
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#include "smscusb.h"
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#include "smsc75xx.h"
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/** Hardware configuration register */
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#define LAN78XX_HW_CFG 0x0010
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#define LAN78XX_HW_CFG_LED1_EN 0x00200000UL /**< LED1 enable */
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#define LAN78XX_HW_CFG_LED0_EN 0x00100000UL /**< LED1 enable */
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#define LAN78XX_HW_CFG_LRST 0x00000002UL /**< Soft lite reset */
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/** Interrupt endpoint control register */
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#define LAN78XX_INT_EP_CTL 0x0098
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#define LAN78XX_INT_EP_CTL_RDFO_EN 0x00400000UL /**< RX FIFO overflow */
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#define LAN78XX_INT_EP_CTL_PHY_EN 0x00020000UL /**< PHY interrupt */
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/** Bulk IN delay register */
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#define LAN78XX_BULK_IN_DLY 0x0094
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#define LAN78XX_BULK_IN_DLY_SET(ticks) ( (ticks) << 0 ) /**< Delay / 16.7ns */
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/** EEPROM register base */
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#define LAN78XX_E2P_BASE 0x0040
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/** USB configuration register 0 */
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#define LAN78XX_USB_CFG0 0x0080
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#define LAN78XX_USB_CFG0_BIR 0x00000040UL /**< Bulk IN use NAK */
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/** Receive filtering engine control register */
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#define LAN78XX_RFE_CTL 0x00b0
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#define LAN78XX_RFE_CTL_AB 0x00000400UL /**< Accept broadcast */
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#define LAN78XX_RFE_CTL_AM 0x00000200UL /**< Accept multicast */
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#define LAN78XX_RFE_CTL_AU 0x00000100UL /**< Accept unicast */
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/** FIFO controller RX FIFO control register */
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#define LAN78XX_FCT_RX_CTL 0x00c0
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#define LAN78XX_FCT_RX_CTL_EN 0x80000000UL /**< FCT RX enable */
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#define LAN78XX_FCT_RX_CTL_BAD 0x02000000UL /**< Store bad frames */
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/** FIFO controller TX FIFO control register */
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#define LAN78XX_FCT_TX_CTL 0x00c4
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#define LAN78XX_FCT_TX_CTL_EN 0x80000000UL /**< FCT TX enable */
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/** MAC control register */
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#define LAN78XX_MAC_CR 0x0100
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#define LAN78XX_MAC_CR_ADP 0x00002000UL /**< Duplex polarity */
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#define LAN78XX_MAC_CR_ADD 0x00001000UL /**< Auto duplex */
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#define LAN78XX_MAC_CR_ASD 0x00000800UL /**< Auto speed */
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/** MAC receive register */
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#define LAN78XX_MAC_RX 0x0104
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#define LAN78XX_MAC_RX_MAX_SIZE(mtu) ( (mtu) << 16 ) /**< Max frame size */
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#define LAN78XX_MAC_RX_MAX_SIZE_DEFAULT \
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LAN78XX_MAC_RX_MAX_SIZE ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ )
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#define LAN78XX_MAC_RX_FCS 0x00000010UL /**< FCS stripping */
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#define LAN78XX_MAC_RX_EN 0x00000001UL /**< RX enable */
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/** MAC transmit register */
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#define LAN78XX_MAC_TX 0x0108
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#define LAN78XX_MAC_TX_EN 0x00000001UL /**< TX enable */
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/** MAC receive address register base */
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#define LAN78XX_RX_ADDR_BASE 0x0118
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/** MII register base */
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#define LAN78XX_MII_BASE 0x0120
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/** PHY interrupt mask MII register */
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#define LAN78XX_MII_PHY_INTR_MASK 25
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/** PHY interrupt source MII register */
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#define LAN78XX_MII_PHY_INTR_SOURCE 26
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/** PHY interrupt: global enable */
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#define LAN78XX_PHY_INTR_ENABLE 0x8000
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/** PHY interrupt: link state change */
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#define LAN78XX_PHY_INTR_LINK 0x2000
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/** PHY interrupt: auto-negotiation failure */
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#define LAN78XX_PHY_INTR_ANEG_ERR 0x0800
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/** PHY interrupt: auto-negotiation complete */
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#define LAN78XX_PHY_INTR_ANEG_DONE 0x0400
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/** MAC address perfect filter register base */
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#define LAN78XX_ADDR_FILT_BASE 0x0400
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/** OTP register base */
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#define LAN78XX_OTP_BASE 0x1000
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/** Maximum time to wait for reset (in milliseconds) */
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#define LAN78XX_RESET_MAX_WAIT_MS 100
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#endif /* _LAN78XX_H */
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