mirror of
https://github.com/ipxe/ipxe
synced 2026-01-10 06:48:47 +03:00
209 lines
6.0 KiB
C
209 lines
6.0 KiB
C
/*
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* Copyright (c) 2008-2011 Atheros Communications Inc.
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*
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* Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
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* Original from Linux kernel 3.0.1
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <ipxe/pci.h>
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#include "ath9k.h"
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static struct pci_device_id ath_pci_id_table[] = {
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PCI_ROM(0x168c, 0x0023, "ar5416", "Atheros 5416 PCI", 0), /* PCI */
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PCI_ROM(0x168c, 0x0024, "ar5416", "Atheros 5416 PCI-E", 0), /* PCI-E */
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PCI_ROM(0x168c, 0x0027, "ar9160", "Atheros 9160 PCI", 0), /* PCI */
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PCI_ROM(0x168c, 0x0029, "ar9280", "Atheros 9280 PCI", 0), /* PCI */
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PCI_ROM(0x168c, 0x002A, "ar9280", "Atheros 9280 PCI-E", 0), /* PCI-E */
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PCI_ROM(0x168c, 0x002B, "ar9285", "Atheros 9285 PCI-E", 0), /* PCI-E */
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PCI_ROM(0x168c, 0x002C, "ar2427", "Atheros 2427 PCI-E", 0), /* PCI-E 802.11n bonded out */
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PCI_ROM(0x168c, 0x002D, "ar9287", "Atheros 9287 PCI", 0), /* PCI */
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PCI_ROM(0x168c, 0x002E, "ar9287", "Atheros 9287 PCI-E", 0), /* PCI-E */
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PCI_ROM(0x168c, 0x0030, "ar9300", "Atheros 9300 PCI-E", 0), /* PCI-E AR9300 */
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PCI_ROM(0x168c, 0x0032, "ar9485", "Atheros 9485 PCI-E", 0), /* PCI-E AR9485 */
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};
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/* return bus cachesize in 4B word units */
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static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
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{
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struct ath_softc *sc = (struct ath_softc *) common->priv;
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u8 u8tmp;
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pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, &u8tmp);
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*csz = (int)u8tmp;
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/*
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* This check was put in to avoid "unpleasant" consequences if
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* the bootrom has not fully initialized all PCI devices.
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* Sometimes the cache line size register is not set
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*/
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if (*csz == 0)
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*csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
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}
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static int ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
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{
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struct ath_hw *ah = (struct ath_hw *) common->ah;
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common->ops->read(ah, AR5416_EEPROM_OFFSET +
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(off << AR5416_EEPROM_S));
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if (!ath9k_hw_wait(ah,
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AR_EEPROM_STATUS_DATA,
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AR_EEPROM_STATUS_DATA_BUSY |
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AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
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AH_WAIT_TIMEOUT)) {
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return 0;
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}
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*data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
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AR_EEPROM_STATUS_DATA_VAL);
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return 1;
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}
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static void ath_pci_extn_synch_enable(struct ath_common *common)
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{
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struct ath_softc *sc = (struct ath_softc *) common->priv;
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struct pci_device *pdev = sc->pdev;
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u8 lnkctl;
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pci_read_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, &lnkctl);
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lnkctl |= 0x0080;
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pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl);
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}
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static const struct ath_bus_ops ath_pci_bus_ops = {
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.ath_bus_type = ATH_PCI,
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.read_cachesize = ath_pci_read_cachesize,
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.eeprom_read = ath_pci_eeprom_read,
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.extn_synch_en = ath_pci_extn_synch_enable,
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};
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static int ath_pci_probe(struct pci_device *pdev)
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{
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void *mem;
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struct ath_softc *sc;
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struct net80211_device *dev;
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u8 csz;
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u16 subsysid;
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u32 val;
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int ret = 0;
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char hw_name[64];
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adjust_pci_device(pdev);
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/*
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* Cache line size is used to size and align various
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* structures used to communicate with the hardware.
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*/
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pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
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if (csz == 0) {
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/*
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* Linux 2.4.18 (at least) writes the cache line size
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* register as a 16-bit wide register which is wrong.
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* We must have this setup properly for rx buffer
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* DMA to work so force a reasonable value here if it
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* comes up zero.
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*/
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csz =16;
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pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
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}
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/*
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* The default setting of latency timer yields poor results,
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* set it to the value used by other systems. It may be worth
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* tweaking this setting more.
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*/
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pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
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/*
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* Disable the RETRY_TIMEOUT register (0x41) to keep
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* PCI Tx retries from interfering with C3 CPU state.
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*/
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pci_read_config_dword(pdev, 0x40, &val);
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if ((val & 0x0000ff00) != 0)
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pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
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mem = ioremap(pdev->membase, 0x10000);
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if (!mem) {
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DBG("ath9K: PCI memory map error\n") ;
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ret = -EIO;
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goto err_iomap;
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}
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dev = net80211_alloc(sizeof(struct ath_softc));
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if (!dev) {
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DBG("ath9k: No memory for net80211_device\n");
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ret = -ENOMEM;
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goto err_alloc_hw;
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}
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pci_set_drvdata(pdev, dev);
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dev->netdev->dev = (struct device *)pdev;
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sc = dev->priv;
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sc->dev = dev;
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sc->pdev = pdev;
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sc->mem = mem;
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/* Will be cleared in ath9k_start() */
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sc->sc_flags |= SC_OP_INVALID;
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sc->irq = pdev->irq;
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pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsysid);
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ret = ath9k_init_device(pdev->device, sc, subsysid, &ath_pci_bus_ops);
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if (ret) {
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DBG("ath9k: Failed to initialize device\n");
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goto err_init;
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}
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ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));
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DBG("ath9k: %s mem=0x%lx, irq=%d\n",
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hw_name, (unsigned long)mem, pdev->irq);
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return 0;
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err_init:
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net80211_free(dev);
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err_alloc_hw:
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iounmap(mem);
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err_iomap:
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return ret;
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}
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static void ath_pci_remove(struct pci_device *pdev)
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{
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struct net80211_device *dev = pci_get_drvdata(pdev);
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struct ath_softc *sc = dev->priv;
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void *mem = sc->mem;
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if (!is_ath9k_unloaded)
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sc->sc_ah->ah_flags |= AH_UNPLUGGED;
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ath9k_deinit_device(sc);
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net80211_free(sc->dev);
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iounmap(mem);
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}
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struct pci_driver ath_pci_driver __pci_driver = {
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.id_count = ARRAY_SIZE(ath_pci_id_table),
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.ids = ath_pci_id_table,
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.probe = ath_pci_probe,
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.remove = ath_pci_remove,
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};
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