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If the virtual address offset is precisely one page (i.e. each virtual address maps to a physical address one page higher), and if the 32-bit transition code happens to end up at the end of a page (which would require an unrealistic 2MB of content in .prefix), then it would be possible for the program counter to cross into the portion of the virtual address space still borrowed for use as the temporary physical map. Avoid this remote possibility by moving the restoration of the temporarily modified PTE within the transition code block (which is guaranteed to remain within a single page since it is aligned on its own size). This unfortunately requires increasing the alignment of the transition code (and hence the maximum number of NOPs inserted). The assembler syntax theoretically allows us to avoid inserting any NOPs via a directive such as: .balign PAGE_SIZE, , enable_paging_32_max_len (i.e. relying on the fact that if the transition code is already sufficiently far away from the end of a page, then no padding needs to be inserted). However, alignment on RISC-V is implemented using the R_RISCV_ALIGN relaxing relocation, which doesn't encode any concept of a maximum padding length, and so the maximum padding length value is effectively ignored. Signed-off-by: Michael Brown <mcb30@ipxe.org>