mirror of
https://github.com/ipxe/ipxe
synced 2025-12-25 00:17:57 +03:00
8406115834
Access to the gpxe.org and etherboot.org domains and associated resources has been revoked by the registrant of the domain. Work around this problem by renaming project from gPXE to iPXE, and updating URLs to match. Also update README, LOG and COPYRIGHTS to remove obsolete information. Signed-off-by: Michael Brown <mcb30@ipxe.org>
87 lines
2.3 KiB
C
87 lines
2.3 KiB
C
FILE_LICENCE ( GPL2_OR_LATER );
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#include <stdint.h>
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#include <ipxe/pci.h>
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/**
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* Look for a PCI capability
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*
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* @v pci PCI device to query
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* @v cap Capability code
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* @ret address Address of capability, or 0 if not found
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*
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* Determine whether or not a device supports a given PCI capability.
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* Returns the address of the requested capability structure within
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* the device's PCI configuration space, or 0 if the device does not
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* support it.
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*/
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int pci_find_capability ( struct pci_device *pci, int cap ) {
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uint16_t status;
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uint8_t pos, id;
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uint8_t hdr_type;
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int ttl = 48;
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pci_read_config_word ( pci, PCI_STATUS, &status );
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if ( ! ( status & PCI_STATUS_CAP_LIST ) )
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return 0;
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pci_read_config_byte ( pci, PCI_HEADER_TYPE, &hdr_type );
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switch ( hdr_type & 0x7F ) {
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case PCI_HEADER_TYPE_NORMAL:
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case PCI_HEADER_TYPE_BRIDGE:
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default:
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pci_read_config_byte ( pci, PCI_CAPABILITY_LIST, &pos );
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break;
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case PCI_HEADER_TYPE_CARDBUS:
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pci_read_config_byte ( pci, PCI_CB_CAPABILITY_LIST, &pos );
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break;
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}
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while ( ttl-- && pos >= 0x40 ) {
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pos &= ~3;
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pci_read_config_byte ( pci, pos + PCI_CAP_LIST_ID, &id );
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DBG ( "PCI Capability: %d\n", id );
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if ( id == 0xff )
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break;
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if ( id == cap )
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return pos;
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pci_read_config_byte ( pci, pos + PCI_CAP_LIST_NEXT, &pos );
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}
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return 0;
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}
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/**
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* Find the size of a PCI BAR
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*
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* @v pci PCI device
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* @v reg PCI register number
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* @ret size BAR size
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*
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* It should not be necessary for any Etherboot code to call this
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* function.
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*/
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unsigned long pci_bar_size ( struct pci_device *pci, unsigned int reg ) {
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uint16_t cmd;
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uint32_t start, size;
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/* Save the original command register */
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pci_read_config_word ( pci, PCI_COMMAND, &cmd );
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/* Save the original bar */
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pci_read_config_dword ( pci, reg, &start );
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/* Compute which bits can be set */
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pci_write_config_dword ( pci, reg, ~0 );
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pci_read_config_dword ( pci, reg, &size );
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/* Restore the original size */
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pci_write_config_dword ( pci, reg, start );
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/* Find the significant bits */
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/* Restore the original command register. This reenables decoding. */
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pci_write_config_word ( pci, PCI_COMMAND, cmd );
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if ( start & PCI_BASE_ADDRESS_SPACE_IO ) {
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size &= PCI_BASE_ADDRESS_IO_MASK;
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} else {
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size &= PCI_BASE_ADDRESS_MEM_MASK;
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}
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/* Find the lowest bit set */
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size = size & ~( size - 1 );
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return size;
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}
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