Michael Brown 06a9330004 [riscv] Add missing volatile qualifiers on timer and seed CSR accesses ...

The timer and entropy seed CSRs will, by design, return different
values each time they are read.

Add the missing volatile qualifiers on the inline assembly to prevent
gcc from assuming that repeated invocations may be elided.

Signed-off-by: Michael Brown <mcb30@ipxe.org>

2024-10-28 16:43:43 +00:00

..

arm

[efi] Centralise definition of efi_cpu_nap()

2024-09-13 14:38:23 +01:00

arm32

[crypto] Use architecture-independent bigint_is_set()

2024-10-10 15:35:16 +01:00

arm64

[crypto] Use architecture-independent bigint_is_set()

2024-10-10 15:35:16 +01:00

i386

[profile] Standardise return type of profile_timestamp()

2024-09-24 15:40:45 +01:00

loong64

[crypto] Use architecture-independent bigint_is_set()

2024-10-10 15:35:16 +01:00

riscv

[riscv] Add missing volatile qualifiers on timer and seed CSR accesses

2024-10-28 16:43:43 +00:00

riscv32

[profile] Standardise return type of profile_timestamp()

2024-09-24 15:40:45 +01:00

riscv64

[profile] Standardise return type of profile_timestamp()

2024-09-24 15:40:45 +01:00

x86

[crypto] Use architecture-independent bigint_is_set()

2024-10-10 15:35:16 +01:00

x86_64

[profile] Standardise return type of profile_timestamp()

2024-09-24 15:40:45 +01:00