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[xhci] Enable USB3 ports on Intel PCH8/PCH9 controllers

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Intel PCH controllers default to routing USB2 ports to EHCI rather
than xHCI, and default to disabling SuperSpeed connections.
Manipulate the PCI configuration space registers as necessary to
reroute ports and enable SuperSpeed.

Originally-fixed-by: Dan Ellis <Dan.Ellis@displaylink.com>
Signed-off-by: Michael Brown <mcb30@ipxe.org>
This commit is contained in:
Michael Brown
2015-03-06 11:41:37 +00:00
parent 1a4e94a828
commit ff320404d5
2 changed files with 55 additions and 0 deletions
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15
src/drivers/usb/xhci.h
View File

@@ -1103,4 +1103,19 @@ struct xhci_endpoint {
struct xhci_trb_ring ring;
};
/** Intel PCH quirk */
#define XHCI_PCH 0x0001
/** Intel PCH USB2 port routing register */
#define XHCI_PCH_XUSB2PR 0xd0
/** Intel PCH USB2 port routing mask register */
#define XHCI_PCH_XUSB2PRM 0xd4
/** Intel PCH USB3 port SuperSpeed enable register */
#define XHCI_PCH_USB3PSSEN 0xd8
/** Intel PCH USB3 port routing mask register */
#define XHCI_PCH_USB3PRM 0xdc
#endif /* _IPXE_XHCI_H */