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[realtek] Support RTL8139 cards within generic Realtek driver
RTL8139C+ cards use essentially the same datapath as RTL8169, which is zerocopy and 64-bit capable. Older RTL8139 cards use a single receive ring buffer rather than a descriptor ring, but still share substantial amounts of functionality with RTL8169. Include support for RTL8139 cards within the generic Realtek driver, since there is no way to differentiate between RTL8139 and RTL8139C+ cards based on the PCI IDs alone. Many thanks to all the people who worked on the rtl8139 driver over the years. Signed-off-by: Michael Brown <mcb30@ipxe.org>
This commit is contained in:
Michael Brown
@@ -49,6 +49,22 @@ enum realtek_descriptor_flags {
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/** Descriptor ring alignment */
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#define RTL_RING_ALIGN 256
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/** A legacy mode receive packet header */
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struct realtek_legacy_header {
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/** Status */
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uint16_t status;
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/** Length */
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uint16_t length;
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/** Packet data */
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uint8_t data[0];
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} __attribute__ (( packed ));
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/** Legacy mode status bits */
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enum realtek_legacy_status {
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/** Received OK */
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RTL_STAT_ROK = 0x0001,
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};
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/** ID Register 0 (6 bytes) */
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#define RTL_IDR0 0x00
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@@ -58,43 +74,75 @@ enum realtek_descriptor_flags {
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/** Multicast Register 4 (dword) */
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#define RTL_MAR4 0x0c
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/** Transmit Status of Descriptor N (dword, 8139 only) */
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#define RTL_TSD(n) ( 0x10 + 4 * (n) )
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#define RTL_TSD_ERTXTH(x) ( (x) << 16 ) /**< Early TX threshold */
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#define RTL_TSD_ERTXTH_DEFAULT RTL_TSD_ERTXTH ( 256 / 32 )
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#define RTL_TSD_OWN 0x00002000UL /**< Ownership */
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/** Transmit Start Address of Descriptor N (dword, 8139 only) */
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#define RTL_TSAD(n) ( 0x20 + 4 * (n) )
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/** Transmit Normal Priority Descriptors (qword) */
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#define RTL_TNPDS 0x20
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/** Number of transmit descriptors */
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/** Number of transmit descriptors
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*
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* This is a hardware limit when using legacy mode.
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*/
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#define RTL_NUM_TX_DESC 4
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/** Receive Buffer Start Address (dword, 8139 only) */
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#define RTL_RBSTART 0x30
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/** Receive buffer length */
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#define RTL_RXBUF_LEN 8192
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/** Receive buffer padding */
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#define RTL_RXBUF_PAD 2038 /* Allow space for WRAP */
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/** Receive buffer alignment */
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#define RTL_RXBUF_ALIGN 16
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/** Command Register (byte) */
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#define RTL_CR 0x37
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#define RTL_CR_RST 0x10 /**< Reset */
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#define RTL_CR_RE 0x08 /**< Receiver Enable */
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#define RTL_CR_TE 0x04 /**< Transmit Enable */
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#define RTL_CR_BUFE 0x01 /**< Receive buffer empty */
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/** Maximum time to wait for a reset, in milliseconds */
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#define RTL_RESET_MAX_WAIT_MS 100
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/** Transmit Priority Polling Register (byte) */
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#define RTL_TPPOLL 0x38
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/** Current Address of Packet Read (word, 8139 only) */
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#define RTL_CAPR 0x38
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/** Transmit Priority Polling Register (byte, 8169 only) */
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#define RTL_TPPOLL_8169 0x38
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#define RTL_TPPOLL_NPQ 0x40 /**< Normal Priority Queue Polling */
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/** Interrupt Mask Register (word) */
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#define RTL_IMR 0x3c
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#define RTL_IRQ_PUN_LINKCHG 0x20 /**< Packet underrun / link change */
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#define RTL_IRQ_TER 0x08 /**< Transmit error */
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#define RTL_IRQ_TOK 0x04 /**< Transmit OK */
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#define RTL_IRQ_RER 0x02 /**< Receive error */
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#define RTL_IRQ_ROK 0x01 /**< Receive OK */
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#define RTL_IRQ_PUN_LINKCHG 0x0020 /**< Packet underrun / link change */
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#define RTL_IRQ_TER 0x0008 /**< Transmit error */
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#define RTL_IRQ_TOK 0x0004 /**< Transmit OK */
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#define RTL_IRQ_RER 0x0002 /**< Receive error */
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#define RTL_IRQ_ROK 0x0001 /**< Receive OK */
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/** Interrupt Status Register (word) */
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#define RTL_ISR 0x3e
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/** Receive (Rx) Configuration Register (dword) */
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#define RTL_RCR 0x44
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#define RTL_RCR_9356SEL 0x40 /**< EEPROM is a 93C56 */
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#define RTL_RCR_AB 0x08 /**< Accept broadcast packets */
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#define RTL_RCR_AM 0x04 /**< Accept multicast packets */
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#define RTL_RCR_APM 0x02 /**< Accept physical match packets */
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#define RTL_RCR_AAP 0x01 /**< Accept all packets */
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#define RTL_RCR_RBLEN(x) ( (x) << 11 ) /**< Receive buffer length */
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#define RTL_RCR_RBLEN_MASK RTL_RCR_RBLEN ( 0x3 )
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#define RTL_RCR_RBLEN_DEFAULT RTL_RCR_RBLEN ( 0 /* 8kB */ )
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#define RTL_RCR_WRAP 0x00000080UL /**< Overrun receive buffer */
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#define RTL_RCR_9356SEL 0x00000040UL /**< EEPROM is a 93C56 */
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#define RTL_RCR_AB 0x00000008UL /**< Accept broadcast packets */
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#define RTL_RCR_AM 0x00000004UL /**< Accept multicast packets */
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#define RTL_RCR_APM 0x00000002UL /**< Accept physical match */
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#define RTL_RCR_AAP 0x00000001UL /**< Accept all packets */
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/** 93C46 (93C56) Command Register (byte) */
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#define RTL_9346CR 0x50
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@@ -118,7 +166,11 @@ enum realtek_descriptor_flags {
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#define RTL_CONFIG1 0x52
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#define RTL_CONFIG1_VPD 0x02 /**< Vital Product Data enabled */
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/** PHY Access Register (dword) */
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/** Media Status Register (byte, 8139 only) */
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#define RTL_MSR 0x58
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#define RTL_MSR_LINKB 0x04 /**< Inverse of link status */
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/** PHY Access Register (dword, 8169 only) */
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#define RTL_PHYAR 0x60
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#define RTL_PHYAR_FLAG 0x80000000UL /**< Read/write flag */
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@@ -131,17 +183,22 @@ enum realtek_descriptor_flags {
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/** Maximum time to wait for PHY access, in microseconds */
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#define RTL_MII_MAX_WAIT_US 500
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/** PHY (GMII, MII, or TBI) Status Register (byte) */
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/** PHY (GMII, MII, or TBI) Status Register (byte, 8169 only) */
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#define RTL_PHYSTATUS 0x6c
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#define RTL_PHYSTATUS_LINKSTS 0x02 /**< Link ok */
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/** Transmit Priority Polling Register (byte, 8139C+ only) */
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#define RTL_TPPOLL_8139CP 0xd9
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/** RX Packet Maximum Size Register (word) */
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#define RTL_RMS 0xda
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/** C+ Command Register (word) */
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#define RTL_CPCR 0xe0
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#define RTL_CPCR_DAC 0x10 /**< PCI Dual Address Cycle Enable */
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#define RTL_CPCR_MULRW 0x08 /**< PCI Multiple Read/Write Enable */
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#define RTL_CPCR_DAC 0x0010 /**< PCI Dual Address Cycle Enable */
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#define RTL_CPCR_MULRW 0x0008 /**< PCI Multiple Read/Write Enable */
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#define RTL_CPCR_CPRX 0x0002 /**< C+ receive enable */
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#define RTL_CPCR_CPTX 0x0001 /**< C+ transmit enable */
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/** Receive Descriptor Start Address Register (qword) */
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#define RTL_RDSAR 0xe4
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@@ -194,12 +251,23 @@ struct realtek_nic {
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/** MII interface */
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struct mii_interface mii;
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/** Legacy datapath mode */
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int legacy;
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/** PHYAR and PHYSTATUS registers are present */
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int have_phy_regs;
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/** TPPoll register offset */
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unsigned int tppoll;
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/** Transmit descriptor ring */
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struct realtek_ring tx;
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/** Receive descriptor ring */
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struct realtek_ring rx;
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/** Receive I/O buffers */
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struct io_buffer *rx_iobuf[RTL_NUM_RX_DESC];
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/** Receive buffer (legacy mode) */
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void *rx_buffer;
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/** Offset within receive buffer (legacy mode) */
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unsigned int rx_offset;
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};
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#endif /* _REALTEK_H */
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