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https://github.com/ipxe/ipxe
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[vxge] Add support for X3100 series 10GbE Server/Storage Adapter
Signed-off-by: Sivakumar Subramani <sivakumar.subramani@neterion.com> Signed-off-by: Masroor Vettuparambil <masroor.vettuparambil@neterion.com> Signed-off-by: Stefan Hajnoczi <stefanha@gmail.com> Signed-off-by: Marty Connor <mdc@etherboot.org>
This commit is contained in:
Masroor Vettuparambil
committed by
Marty Connor
Marty Connor
parent
b7af0aa34e
commit
f5f8ee00fc
309
src/drivers/net/vxge/vxge_traffic.h
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309
src/drivers/net/vxge/vxge_traffic.h
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/*
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* vxge-traffic.h: gPXE driver for Neterion Inc's X3100 Series 10GbE
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* PCIe I/O Virtualized Server Adapter.
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*
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* Copyright(c) 2002-2010 Neterion Inc.
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*
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* This software may be used and distributed according to the terms of
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* the GNU General Public License (GPL), incorporated herein by
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* reference. Drivers based on or derived from this code fall under
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* the GPL and must retain the authorship, copyright and license
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* notice.
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*
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*/
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FILE_LICENCE(GPL2_ONLY);
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#ifndef VXGE_TRAFFIC_H
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#define VXGE_TRAFFIC_H
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#include <stdint.h>
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#include <gpxe/if_ether.h>
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#include <gpxe/iobuf.h>
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#include "vxge_reg.h"
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#include "vxge_version.h"
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#define VXGE_HW_DTR_MAX_T_CODE 16
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#define VXGE_HW_ALL_FOXES 0xFFFFFFFFFFFFFFFFULL
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#define VXGE_HW_INTR_MASK_ALL 0xFFFFFFFFFFFFFFFFULL
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#define VXGE_HW_MAX_VIRTUAL_PATHS 17
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#define VXGE_HW_MAX_VIRTUAL_FUNCTIONS 8
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#define VXGE_HW_MAC_MAX_MAC_PORT_ID 3
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#define VXGE_HW_DEFAULT_32 0xffffffff
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/* frames sizes */
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#define VXGE_HW_HEADER_802_2_SIZE 3
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#define VXGE_HW_HEADER_SNAP_SIZE 5
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#define VXGE_HW_HEADER_VLAN_SIZE 4
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#define VXGE_HW_MAC_HEADER_MAX_SIZE \
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(ETH_HLEN + \
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VXGE_HW_HEADER_802_2_SIZE + \
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VXGE_HW_HEADER_VLAN_SIZE + \
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VXGE_HW_HEADER_SNAP_SIZE)
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/* 32bit alignments */
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/* A receive data corruption can occur resulting in either a single-bit or
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double-bit ECC error being flagged in the ASIC if the starting offset of a
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buffer in single buffer mode is 0x2 to 0xa. The single bit ECC error will not
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lock up the card but can hide the data corruption while the double-bit ECC
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error will lock up the card. Limiting the starting offset of the buffers to
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0x0, 0x1 or to a value greater than 0xF will workaround this issue.
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VXGE_HW_HEADER_ETHERNET_II_802_3_ALIGN of 2 causes the starting offset of
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buffer to be 0x2, 0x12 and so on, to have the start of the ip header dword
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aligned. The start of buffer of 0x2 will cause this problem to occur. To
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avoid this problem in all cases, add 0x10 to 0x2, to ensure that the start of
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buffer is outside of the problem causing offsets.
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*/
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#define VXGE_HW_HEADER_ETHERNET_II_802_3_ALIGN 0x12
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#define VXGE_HW_HEADER_802_2_SNAP_ALIGN 2
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#define VXGE_HW_HEADER_802_2_ALIGN 3
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#define VXGE_HW_HEADER_SNAP_ALIGN 1
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#define VXGE_HW_L3_CKSUM_OK 0xFFFF
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#define VXGE_HW_L4_CKSUM_OK 0xFFFF
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/* Forward declarations */
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struct __vxge_hw_device;
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struct __vxge_hw_virtualpath;
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struct __vxge_hw_fifo;
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struct __vxge_hw_ring;
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struct vxge_hw_ring_rxd_1;
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struct vxge_hw_fifo_txd;
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#ifndef TRUE
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#define TRUE 1
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#endif
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#ifndef FALSE
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#define FALSE 0
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#endif
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/*VXGE_HW_STATUS_H*/
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#define VXGE_HW_EVENT_BASE 0
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#define VXGE_LL_EVENT_BASE 100
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/**
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* enum vxge_hw_event- Enumerates slow-path HW events.
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* @VXGE_HW_EVENT_UNKNOWN: Unknown (and invalid) event.
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* @VXGE_HW_EVENT_SERR: Serious vpath hardware error event.
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* @VXGE_HW_EVENT_ECCERR: vpath ECC error event.
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* @VXGE_HW_EVENT_VPATH_ERR: Error local to the respective vpath
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* @VXGE_HW_EVENT_FIFO_ERR: FIFO Doorbell fifo error.
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* @VXGE_HW_EVENT_SRPCIM_SERR: srpcim hardware error event.
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* @VXGE_HW_EVENT_MRPCIM_SERR: mrpcim hardware error event.
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* @VXGE_HW_EVENT_MRPCIM_ECCERR: mrpcim ecc error event.
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* @VXGE_HW_EVENT_RESET_START: Privileged entity is starting device reset
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* @VXGE_HW_EVENT_RESET_COMPLETE: Device reset has been completed
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* @VXGE_HW_EVENT_SLOT_FREEZE: Slot-freeze event. Driver tries to distinguish
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* slot-freeze from the rest critical events (e.g. ECC) when it is
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* impossible to PIO read "through" the bus, i.e. when getting all-foxes.
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*
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* enum vxge_hw_event enumerates slow-path HW eventis.
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*
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* See also: struct vxge_hw_uld_cbs{}, vxge_uld_link_up_f{},
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* vxge_uld_link_down_f{}.
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*/
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enum vxge_hw_event {
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VXGE_HW_EVENT_UNKNOWN = 0,
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/* HW events */
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VXGE_HW_EVENT_RESET_START = VXGE_HW_EVENT_BASE + 1,
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VXGE_HW_EVENT_RESET_COMPLETE = VXGE_HW_EVENT_BASE + 2,
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VXGE_HW_EVENT_LINK_DOWN = VXGE_HW_EVENT_BASE + 3,
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VXGE_HW_EVENT_LINK_UP = VXGE_HW_EVENT_BASE + 4,
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VXGE_HW_EVENT_ALARM_CLEARED = VXGE_HW_EVENT_BASE + 5,
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VXGE_HW_EVENT_ECCERR = VXGE_HW_EVENT_BASE + 6,
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VXGE_HW_EVENT_MRPCIM_ECCERR = VXGE_HW_EVENT_BASE + 7,
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VXGE_HW_EVENT_FIFO_ERR = VXGE_HW_EVENT_BASE + 8,
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VXGE_HW_EVENT_VPATH_ERR = VXGE_HW_EVENT_BASE + 9,
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VXGE_HW_EVENT_CRITICAL_ERR = VXGE_HW_EVENT_BASE + 10,
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VXGE_HW_EVENT_SERR = VXGE_HW_EVENT_BASE + 11,
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VXGE_HW_EVENT_SRPCIM_SERR = VXGE_HW_EVENT_BASE + 12,
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VXGE_HW_EVENT_MRPCIM_SERR = VXGE_HW_EVENT_BASE + 13,
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VXGE_HW_EVENT_SLOT_FREEZE = VXGE_HW_EVENT_BASE + 14,
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};
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#define VXGE_HW_MAX_INTR_PER_VP 4
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#define VXGE_HW_VPATH_INTR_TX 0
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#define VXGE_HW_VPATH_INTR_RX 1
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#define VXGE_HW_VPATH_INTR_EINTA 2
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#define VXGE_HW_VPATH_INTR_BMAP 3
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#define VXGE_HW_BLOCK_SIZE 4096
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#define VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL 17
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#define VXGE_HW_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL 18
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#define VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_RX_AVE_NET_UTIL 19
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#define VXGE_HW_TIM_UTIL_SEL_PER_VPATH 63
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/**
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* enum vxge_hw_ring_tcode - Transfer codes returned by adapter
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* @VXGE_HW_RING_T_CODE_OK: Transfer ok.
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* @VXGE_HW_RING_T_CODE_L3_CKSUM_MISMATCH: Layer 3 checksum presentation
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* configuration mismatch.
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* @VXGE_HW_RING_T_CODE_L4_CKSUM_MISMATCH: Layer 4 checksum presentation
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* configuration mismatch.
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* @VXGE_HW_RING_T_CODE_L3_L4_CKSUM_MISMATCH: Layer 3 and Layer 4 checksum
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* presentation configuration mismatch.
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* @VXGE_HW_RING_T_CODE_L3_PKT_ERR: Layer 3 error unparseable packet,
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* such as unknown IPv6 header.
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* @VXGE_HW_RING_T_CODE_L2_FRM_ERR: Layer 2 error frame integrity
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* error, such as FCS or ECC).
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* @VXGE_HW_RING_T_CODE_BUF_SIZE_ERR: Buffer size error the RxD buffer(
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* s) were not appropriately sized and data loss occurred.
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* @VXGE_HW_RING_T_CODE_INT_ECC_ERR: Internal ECC error RxD corrupted.
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* @VXGE_HW_RING_T_CODE_BENIGN_OVFLOW: Benign overflow the contents of
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* Segment1 exceeded the capacity of Buffer1 and the remainder
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* was placed in Buffer2. Segment2 now starts in Buffer3.
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* No data loss or errors occurred.
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* @VXGE_HW_RING_T_CODE_ZERO_LEN_BUFF: Buffer size 0 one of the RxDs
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* assigned buffers has a size of 0 bytes.
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* @VXGE_HW_RING_T_CODE_FRM_DROP: Frame dropped either due to
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* VPath Reset or because of a VPIN mismatch.
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* @VXGE_HW_RING_T_CODE_UNUSED: Unused
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* @VXGE_HW_RING_T_CODE_MULTI_ERR: Multiple errors more than one
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* transfer code condition occurred.
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*
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* Transfer codes returned by adapter.
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*/
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enum vxge_hw_ring_tcode {
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VXGE_HW_RING_T_CODE_OK = 0x0,
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VXGE_HW_RING_T_CODE_L3_CKSUM_MISMATCH = 0x1,
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VXGE_HW_RING_T_CODE_L4_CKSUM_MISMATCH = 0x2,
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VXGE_HW_RING_T_CODE_L3_L4_CKSUM_MISMATCH = 0x3,
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VXGE_HW_RING_T_CODE_L3_PKT_ERR = 0x5,
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VXGE_HW_RING_T_CODE_L2_FRM_ERR = 0x6,
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VXGE_HW_RING_T_CODE_BUF_SIZE_ERR = 0x7,
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VXGE_HW_RING_T_CODE_INT_ECC_ERR = 0x8,
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VXGE_HW_RING_T_CODE_BENIGN_OVFLOW = 0x9,
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VXGE_HW_RING_T_CODE_ZERO_LEN_BUFF = 0xA,
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VXGE_HW_RING_T_CODE_FRM_DROP = 0xC,
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VXGE_HW_RING_T_CODE_UNUSED = 0xE,
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VXGE_HW_RING_T_CODE_MULTI_ERR = 0xF
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};
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/**
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* enum enum vxge_hw_fifo_gather_code - Gather codes used in fifo TxD
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* @VXGE_HW_FIFO_GATHER_CODE_FIRST: First TxDL
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* @VXGE_HW_FIFO_GATHER_CODE_MIDDLE: Middle TxDL
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* @VXGE_HW_FIFO_GATHER_CODE_LAST: Last TxDL
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* @VXGE_HW_FIFO_GATHER_CODE_FIRST_LAST: First and Last TxDL.
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*
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* These gather codes are used to indicate the position of a TxD in a TxD list
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*/
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enum vxge_hw_fifo_gather_code {
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VXGE_HW_FIFO_GATHER_CODE_FIRST = 0x2,
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VXGE_HW_FIFO_GATHER_CODE_MIDDLE = 0x0,
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VXGE_HW_FIFO_GATHER_CODE_LAST = 0x1,
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VXGE_HW_FIFO_GATHER_CODE_FIRST_LAST = 0x3
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};
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/**
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* enum enum vxge_hw_fifo_tcode - tcodes used in fifo
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* @VXGE_HW_FIFO_T_CODE_OK: Transfer OK
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* @VXGE_HW_FIFO_T_CODE_PCI_READ_CORRUPT: PCI read transaction (either TxD or
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* frame data) returned with corrupt data.
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* @VXGE_HW_FIFO_T_CODE_PCI_READ_FAIL:PCI read transaction was returned
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* with no data.
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* @VXGE_HW_FIFO_T_CODE_INVALID_MSS: The host attempted to send either a
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* frame or LSO MSS that was too long (>9800B).
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* @VXGE_HW_FIFO_T_CODE_LSO_ERROR: Error detected during TCP/UDP Large Send
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* Offload operation, due to improper header template,
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* unsupported protocol, etc.
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* @VXGE_HW_FIFO_T_CODE_UNUSED: Unused
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* @VXGE_HW_FIFO_T_CODE_MULTI_ERROR: Set to 1 by the adapter if multiple
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* data buffer transfer errors are encountered (see below).
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* Otherwise it is set to 0.
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*
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* These tcodes are returned in various API for TxD status
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*/
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enum vxge_hw_fifo_tcode {
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VXGE_HW_FIFO_T_CODE_OK = 0x0,
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VXGE_HW_FIFO_T_CODE_PCI_READ_CORRUPT = 0x1,
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VXGE_HW_FIFO_T_CODE_PCI_READ_FAIL = 0x2,
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VXGE_HW_FIFO_T_CODE_INVALID_MSS = 0x3,
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VXGE_HW_FIFO_T_CODE_LSO_ERROR = 0x4,
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VXGE_HW_FIFO_T_CODE_UNUSED = 0x7,
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VXGE_HW_FIFO_T_CODE_MULTI_ERROR = 0x8
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};
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enum vxge_hw_status
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vxge_hw_ring_replenish(struct __vxge_hw_ring *ring);
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void vxge_hw_ring_rxd_post(struct __vxge_hw_ring *ring_handle,
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struct vxge_hw_ring_rxd_1 *rxdp);
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void vxge_hw_fifo_txdl_buffer_set(struct __vxge_hw_fifo *fifo,
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struct vxge_hw_fifo_txd *txdp,
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struct io_buffer *iob);
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void vxge_hw_fifo_txdl_post(struct __vxge_hw_fifo *fifo,
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struct vxge_hw_fifo_txd *txdp);
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enum vxge_hw_status __vxge_hw_ring_create(
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struct __vxge_hw_virtualpath *vpath,
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struct __vxge_hw_ring *ring);
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enum vxge_hw_status __vxge_hw_ring_delete(
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struct __vxge_hw_ring *ringh);
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enum vxge_hw_status __vxge_hw_fifo_create(
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struct __vxge_hw_virtualpath *vpath,
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struct __vxge_hw_fifo *fifo);
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enum vxge_hw_status
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__vxge_hw_fifo_delete(struct __vxge_hw_fifo *fifo);
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enum vxge_hw_status __vxge_hw_vpath_reset(
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struct __vxge_hw_device *devh, u32 vp_id);
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enum vxge_hw_status
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__vxge_hw_vpath_enable(struct __vxge_hw_device *devh, u32 vp_id);
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void
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__vxge_hw_vpath_prc_configure(struct __vxge_hw_device *hldev);
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enum vxge_hw_status
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__vxge_hw_vpath_kdfc_configure(struct __vxge_hw_device *devh, u32 vp_id);
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enum vxge_hw_status
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__vxge_hw_vpath_mac_configure(struct __vxge_hw_device *devh);
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enum vxge_hw_status
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__vxge_hw_vpath_tim_configure(struct __vxge_hw_device *devh, u32 vp_id);
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enum vxge_hw_status
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__vxge_hw_vpath_initialize(struct __vxge_hw_device *devh, u32 vp_id);
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enum vxge_hw_status __vxge_hw_vp_initialize(
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struct __vxge_hw_device *hldev, u32 vp_id,
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struct __vxge_hw_virtualpath *vpath);
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void __vxge_hw_vp_terminate(struct __vxge_hw_device *hldev,
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struct __vxge_hw_virtualpath *vpath);
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enum vxge_hw_status
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vxge_hw_device_begin_irq(struct __vxge_hw_device *hldev);
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void vxge_hw_device_intr_enable(struct __vxge_hw_device *hldev);
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void vxge_hw_device_intr_disable(struct __vxge_hw_device *hldev);
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void vxge_hw_device_mask_all(struct __vxge_hw_device *hldev);
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void vxge_hw_device_unmask_all(struct __vxge_hw_device *hldev);
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void vxge_hw_vpath_doorbell_rx(struct __vxge_hw_ring *ringh);
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enum vxge_hw_status vxge_hw_vpath_poll_rx(struct __vxge_hw_ring *ringh);
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enum vxge_hw_status vxge_hw_vpath_poll_tx(struct __vxge_hw_fifo *fifo);
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struct vxge_hw_fifo_txd *
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vxge_hw_fifo_free_txdl_get(struct __vxge_hw_fifo *fifo);
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#endif
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