mirror of
https://github.com/ipxe/ipxe
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[sfc] Add driver for Solarflare SFC8XXX adapters
Signed-off-by: Martin Habets <mhabets@solarflare.com> Modified-by: Michael Brown <mcb30@ipxe.org> Signed-off-by: Michael Brown <mcb30@ipxe.org>
This commit is contained in:
Martin Habets
committed by
Michael Brown
Michael Brown
parent
ffb5fe4ced
commit
f3788fa837
510
src/drivers/net/sfc/efx_hunt.c
Normal file
510
src/drivers/net/sfc/efx_hunt.c
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@@ -0,0 +1,510 @@
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/**************************************************************************
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*
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* Driver datapath for Solarflare network cards
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*
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* Written by Shradha Shah <sshah@solarflare.com>
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*
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* Copyright 2012-2017 Solarflare Communications Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or any later version.
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*
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* You can also choose to distribute this program under the terms of
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* the Unmodified Binary Distribution Licence (as given in the file
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* COPYING.UBDL), provided that you have satisfied its requirements.
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*
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***************************************************************************/
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#include <stdint.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <unistd.h>
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#include <errno.h>
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#include <assert.h>
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#include <byteswap.h>
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#include <ipxe/io.h>
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#include <ipxe/pci.h>
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#include <ipxe/malloc.h>
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#include <ipxe/iobuf.h>
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#include <ipxe/netdevice.h>
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#include "efx_hunt.h"
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#include "efx_bitfield.h"
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#include "ef10_regs.h"
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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void efx_hunt_free_special_buffer(void *buf, int bytes)
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{
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free_dma(buf, bytes);
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}
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static void *efx_hunt_alloc_special_buffer(int bytes,
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struct efx_special_buffer *entry)
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{
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void *buffer;
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dma_addr_t dma_addr;
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/* Allocate the buffer, aligned on a buffer address boundary. This
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* buffer will be passed into an MC_CMD_INIT_*Q command to setup the
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* appropriate type of queue via MCDI.
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*/
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buffer = malloc_dma(bytes, EFX_BUF_ALIGN);
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if (!buffer)
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return NULL;
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entry->dma_addr = dma_addr = virt_to_bus(buffer);
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assert((dma_addr & (EFX_BUF_ALIGN - 1)) == 0);
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/* Buffer table entries aren't allocated, so set id to zero */
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entry->id = 0;
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DBGP("Allocated 0x%x bytes at %p\n", bytes, buffer);
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return buffer;
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}
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/*******************************************************************************
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*
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*
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* TX
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*
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*
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******************************************************************************/
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static void
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efx_hunt_build_tx_desc(efx_tx_desc_t *txd, struct io_buffer *iob)
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{
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dma_addr_t dma_addr;
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dma_addr = virt_to_bus(iob->data);
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EFX_POPULATE_QWORD_4(*txd,
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ESF_DZ_TX_KER_TYPE, 0,
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ESF_DZ_TX_KER_CONT, 0,
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ESF_DZ_TX_KER_BYTE_CNT, iob_len(iob),
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ESF_DZ_TX_KER_BUF_ADDR, dma_addr);
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}
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static void
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efx_hunt_notify_tx_desc(struct efx_nic *efx)
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{
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struct efx_tx_queue *txq = &efx->txq;
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int ptr = txq->write_ptr & EFX_TXD_MASK;
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efx_dword_t reg;
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EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, ptr);
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efx_writel_page(efx, ®, 0, ER_DZ_TX_DESC_UPD_DWORD);
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}
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int
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efx_hunt_transmit(struct net_device *netdev, struct io_buffer *iob)
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{
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struct efx_nic *efx = netdev_priv(netdev);
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struct efx_tx_queue *txq = &efx->txq;
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int fill_level, space;
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efx_tx_desc_t *txd;
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int buf_id;
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fill_level = txq->write_ptr - txq->read_ptr;
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space = EFX_TXD_SIZE - fill_level - 1;
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if (space < 1)
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return -ENOBUFS;
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/* Save the iobuffer for later completion */
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buf_id = txq->write_ptr & EFX_TXD_MASK;
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assert(txq->buf[buf_id] == NULL);
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txq->buf[buf_id] = iob;
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DBGCIO(efx, "tx_buf[%d] for iob %p data %p len %zd\n",
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buf_id, iob, iob->data, iob_len(iob));
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/* Form the descriptor, and push it to hardware */
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txd = txq->ring + buf_id;
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efx_hunt_build_tx_desc(txd, iob);
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++txq->write_ptr;
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efx_hunt_notify_tx_desc(efx);
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return 0;
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}
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static void
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efx_hunt_transmit_done(struct efx_nic *efx, int id)
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{
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struct efx_tx_queue *txq = &efx->txq;
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unsigned int read_ptr, stop;
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/* Complete all buffers from read_ptr up to and including id */
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read_ptr = txq->read_ptr & EFX_TXD_MASK;
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stop = (id + 1) & EFX_TXD_MASK;
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while (read_ptr != stop) {
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struct io_buffer *iob = txq->buf[read_ptr];
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assert(iob);
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/* Complete the tx buffer */
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if (iob)
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netdev_tx_complete(efx->netdev, iob);
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DBGCIO(efx, "tx_buf[%d] for iob %p done\n", read_ptr, iob);
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txq->buf[read_ptr] = NULL;
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++txq->read_ptr;
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read_ptr = txq->read_ptr & EFX_TXD_MASK;
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}
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}
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int efx_hunt_tx_init(struct net_device *netdev, dma_addr_t *dma_addr)
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{
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struct efx_nic *efx = netdev_priv(netdev);
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struct efx_tx_queue *txq = &efx->txq;
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size_t bytes;
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/* Allocate hardware transmit queue */
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bytes = sizeof(efx_tx_desc_t) * EFX_TXD_SIZE;
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txq->ring = efx_hunt_alloc_special_buffer(bytes, &txq->entry);
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if (!txq->ring)
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return -ENOMEM;
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txq->read_ptr = txq->write_ptr = 0;
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*dma_addr = txq->entry.dma_addr;
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return 0;
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}
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/*******************************************************************************
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*
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*
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* RX
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*
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*
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******************************************************************************/
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static void
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efx_hunt_build_rx_desc(efx_rx_desc_t *rxd, struct io_buffer *iob)
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{
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dma_addr_t dma_addr = virt_to_bus(iob->data);
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EFX_POPULATE_QWORD_2(*rxd,
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ESF_DZ_RX_KER_BYTE_CNT, EFX_RX_BUF_SIZE,
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ESF_DZ_RX_KER_BUF_ADDR, dma_addr);
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}
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static void
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efx_hunt_notify_rx_desc(struct efx_nic *efx)
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{
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struct efx_rx_queue *rxq = &efx->rxq;
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int ptr = rxq->write_ptr & EFX_RXD_MASK;
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efx_dword_t reg;
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EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR, ptr);
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efx_writel_page(efx, ®, 0, ER_DZ_RX_DESC_UPD);
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}
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static void
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efx_hunt_rxq_fill(struct efx_nic *efx)
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{
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struct efx_rx_queue *rxq = &efx->rxq;
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int fill_level = rxq->write_ptr - rxq->read_ptr;
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int space = EFX_NUM_RX_DESC - fill_level - 1;
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int pushed = 0;
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while (space) {
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int buf_id = rxq->write_ptr & (EFX_NUM_RX_DESC - 1);
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int desc_id = rxq->write_ptr & EFX_RXD_MASK;
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struct io_buffer *iob;
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efx_rx_desc_t *rxd;
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assert(rxq->buf[buf_id] == NULL);
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iob = alloc_iob(EFX_RX_BUF_SIZE);
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if (!iob)
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break;
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DBGCP(efx, "pushing rx_buf[%d] iob %p data %p\n",
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buf_id, iob, iob->data);
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rxq->buf[buf_id] = iob;
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rxd = rxq->ring + desc_id;
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efx_hunt_build_rx_desc(rxd, iob);
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++rxq->write_ptr;
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++pushed;
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--space;
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}
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/* Push the ptr to hardware */
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if (pushed > 0) {
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efx_hunt_notify_rx_desc(efx);
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DBGCP(efx, "pushed %d rx buffers to fill level %d\n",
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pushed, rxq->write_ptr - rxq->read_ptr);
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}
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}
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static void
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efx_hunt_receive(struct efx_nic *efx, unsigned int id, int len, int drop)
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{
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struct efx_rx_queue *rxq = &efx->rxq;
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unsigned int read_ptr = rxq->read_ptr & EFX_RXD_MASK;
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unsigned int buf_ptr = rxq->read_ptr & EFX_NUM_RX_DESC_MASK;
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struct io_buffer *iob;
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/* id is the lower 4 bits of the desc index + 1 in huntington*/
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/* hence anding with 15 */
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assert((id & 15) == ((read_ptr + (len != 0)) & 15));
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/* Pop this rx buffer out of the software ring */
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iob = rxq->buf[buf_ptr];
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rxq->buf[buf_ptr] = NULL;
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DBGCIO(efx, "popping rx_buf[%d] iob %p data %p with %d bytes %s %x\n",
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read_ptr, iob, iob->data, len, drop ? "bad" : "ok", drop);
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/* Pass the packet up if required */
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if (drop)
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netdev_rx_err(efx->netdev, iob, EBADMSG);
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else {
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iob_put(iob, len);
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iob_pull(iob, efx->rx_prefix_size);
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netdev_rx(efx->netdev, iob);
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}
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++rxq->read_ptr;
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}
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int efx_hunt_rx_init(struct net_device *netdev, dma_addr_t *dma_addr)
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{
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struct efx_nic *efx = netdev_priv(netdev);
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struct efx_rx_queue *rxq = &efx->rxq;
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size_t bytes;
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/* Allocate hardware receive queue */
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bytes = sizeof(efx_rx_desc_t) * EFX_RXD_SIZE;
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rxq->ring = efx_hunt_alloc_special_buffer(bytes, &rxq->entry);
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if (rxq->ring == NULL)
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return -ENOMEM;
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rxq->read_ptr = rxq->write_ptr = 0;
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*dma_addr = rxq->entry.dma_addr;
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return 0;
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}
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/*******************************************************************************
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*
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*
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* Event queues and interrupts
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*
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*
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******************************************************************************/
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int efx_hunt_ev_init(struct net_device *netdev, dma_addr_t *dma_addr)
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{
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struct efx_nic *efx = netdev_priv(netdev);
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struct efx_ev_queue *evq = &efx->evq;
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size_t bytes;
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/* Allocate the hardware event queue */
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bytes = sizeof(efx_event_t) * EFX_EVQ_SIZE;
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evq->ring = efx_hunt_alloc_special_buffer(bytes, &evq->entry);
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if (evq->ring == NULL)
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return -ENOMEM;
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memset(evq->ring, 0xff, bytes);
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evq->read_ptr = 0;
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*dma_addr = evq->entry.dma_addr;
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return 0;
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}
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static void
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efx_hunt_clear_interrupts(struct efx_nic *efx)
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{
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efx_dword_t reg;
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/* read the ISR */
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efx_readl(efx, ®, ER_DZ_BIU_INT_ISR);
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}
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/**
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* See if an event is present
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*
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* @v event EFX event structure
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* @ret True An event is pending
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* @ret False No event is pending
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*
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* We check both the high and low dword of the event for all ones. We
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* wrote all ones when we cleared the event, and no valid event can
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* have all ones in either its high or low dwords. This approach is
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* robust against reordering.
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*
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* Note that using a single 64-bit comparison is incorrect; even
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* though the CPU read will be atomic, the DMA write may not be.
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*/
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static inline int
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efx_hunt_event_present(efx_event_t *event)
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{
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return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
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EFX_DWORD_IS_ALL_ONES(event->dword[1])));
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}
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static void
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efx_hunt_evq_read_ack(struct efx_nic *efx)
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{
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struct efx_ev_queue *evq = &efx->evq;
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efx_dword_t reg;
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if (efx->workaround_35388) {
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EFX_POPULATE_DWORD_2(reg, ERF_DD_EVQ_IND_RPTR_FLAGS,
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EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
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ERF_DD_EVQ_IND_RPTR,
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evq->read_ptr >> ERF_DD_EVQ_IND_RPTR_WIDTH);
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efx_writel_page(efx, ®, 0, ER_DD_EVQ_INDIRECT);
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EFX_POPULATE_DWORD_2(reg, ERF_DD_EVQ_IND_RPTR_FLAGS,
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EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
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ERF_DD_EVQ_IND_RPTR, evq->read_ptr &
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((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
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efx_writel_page(efx, ®, 0, ER_DD_EVQ_INDIRECT);
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} else {
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EFX_POPULATE_DWORD_1(reg, ERF_DZ_EVQ_RPTR, evq->read_ptr);
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efx_writel_table(efx, ®, 0, ER_DZ_EVQ_RPTR);
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}
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}
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static unsigned int
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efx_hunt_handle_event(struct efx_nic *efx, efx_event_t *evt)
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{
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struct efx_rx_queue *rxq = &efx->rxq;
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int ev_code, desc_ptr, len;
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int next_ptr_lbits, packet_drop;
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int rx_cont;
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/* Decode event */
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ev_code = EFX_QWORD_FIELD(*evt, ESF_DZ_EV_CODE);
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switch (ev_code) {
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case ESE_DZ_EV_CODE_TX_EV:
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desc_ptr = EFX_QWORD_FIELD(*evt, ESF_DZ_TX_DESCR_INDX);
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efx_hunt_transmit_done(efx, desc_ptr);
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break;
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case ESE_DZ_EV_CODE_RX_EV:
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len = EFX_QWORD_FIELD(*evt, ESF_DZ_RX_BYTES);
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next_ptr_lbits = EFX_QWORD_FIELD(*evt, ESF_DZ_RX_DSC_PTR_LBITS);
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rx_cont = EFX_QWORD_FIELD(*evt, ESF_DZ_RX_CONT);
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/* We don't expect to receive scattered packets, so drop the
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* packet if RX_CONT is set on the current or previous event, or
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* if len is zero.
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*/
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packet_drop = (len == 0) | (rx_cont << 1) |
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(rxq->rx_cont_prev << 2);
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efx_hunt_receive(efx, next_ptr_lbits, len, packet_drop);
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rxq->rx_cont_prev = rx_cont;
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return 1;
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default:
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DBGCP(efx, "Unknown event type %d\n", ev_code);
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break;
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}
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return 0;
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}
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void efx_hunt_poll(struct net_device *netdev)
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{
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struct efx_nic *efx = netdev_priv(netdev);
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struct efx_ev_queue *evq = &efx->evq;
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efx_event_t *evt;
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int budget = 10;
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/* Read the event queue by directly looking for events
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* (we don't even bother to read the eventq write ptr)
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*/
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evt = evq->ring + evq->read_ptr;
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while (efx_hunt_event_present(evt) && (budget > 0)) {
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DBGCP(efx, "Event at index 0x%x address %p is "
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EFX_QWORD_FMT "\n", evq->read_ptr,
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evt, EFX_QWORD_VAL(*evt));
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budget -= efx_hunt_handle_event(efx, evt);
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/* Clear the event */
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EFX_SET_QWORD(*evt);
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/* Move to the next event. We don't ack the event
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* queue until the end
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*/
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evq->read_ptr = ((evq->read_ptr + 1) & EFX_EVQ_MASK);
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evt = evq->ring + evq->read_ptr;
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}
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/* Push more rx buffers if needed */
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efx_hunt_rxq_fill(efx);
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/* Clear any pending interrupts */
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efx_hunt_clear_interrupts(efx);
|
||||
|
||||
/* Ack the event queue if interrupts are enabled */
|
||||
if (efx->int_en)
|
||||
efx_hunt_evq_read_ack(efx);
|
||||
}
|
||||
|
||||
void efx_hunt_irq(struct net_device *netdev, int enable)
|
||||
{
|
||||
struct efx_nic *efx = netdev_priv(netdev);
|
||||
|
||||
efx->int_en = enable;
|
||||
|
||||
/* If interrupts are enabled, prime the event queue. Otherwise ack any
|
||||
* pending interrupts
|
||||
*/
|
||||
if (enable)
|
||||
efx_hunt_evq_read_ack(efx);
|
||||
else if (efx->netdev->state & NETDEV_OPEN)
|
||||
efx_hunt_clear_interrupts(efx);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
*
|
||||
* Initialization and Close
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
int efx_hunt_open(struct net_device *netdev)
|
||||
{
|
||||
struct efx_nic *efx = netdev_priv(netdev);
|
||||
efx_dword_t cmd;
|
||||
|
||||
/* Set interrupt moderation to 0*/
|
||||
EFX_POPULATE_DWORD_2(cmd,
|
||||
ERF_DZ_TC_TIMER_MODE, 0,
|
||||
ERF_DZ_TC_TIMER_VAL, 0);
|
||||
efx_writel_page(efx, &cmd, 0, ER_DZ_EVQ_TMR);
|
||||
|
||||
/* Ack the eventq */
|
||||
if (efx->int_en)
|
||||
efx_hunt_evq_read_ack(efx);
|
||||
|
||||
/* Push receive buffers */
|
||||
efx_hunt_rxq_fill(efx);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void efx_hunt_close(struct net_device *netdev)
|
||||
{
|
||||
struct efx_nic *efx = netdev_priv(netdev);
|
||||
struct efx_rx_queue *rxq = &efx->rxq;
|
||||
struct efx_tx_queue *txq = &efx->txq;
|
||||
int i;
|
||||
|
||||
/* Complete outstanding descriptors */
|
||||
for (i = 0; i < EFX_NUM_RX_DESC; i++) {
|
||||
if (rxq->buf[i]) {
|
||||
free_iob(rxq->buf[i]);
|
||||
rxq->buf[i] = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < EFX_TXD_SIZE; i++) {
|
||||
if (txq->buf[i]) {
|
||||
netdev_tx_complete(efx->netdev, txq->buf[i]);
|
||||
txq->buf[i] = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
/* Clear interrupts */
|
||||
efx_hunt_clear_interrupts(efx);
|
||||
}
|
||||
Reference in New Issue
Block a user