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[pci] Add definitions for PCI Express function level reset (FLR)

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Signed-off-by: Michael Brown <mcb30@ipxe.org>
This commit is contained in:
Michael Brown
2015-11-25 09:32:45 +00:00
parent 475cc92b0b
commit ed18cd5678
2 changed files with 7 additions and 1 deletions
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1
src/drivers/net/tg3/tg3.h
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@@ -52,7 +52,6 @@
#define PCI_X_CMD 2 /* Modes & Features */ #define PCI_X_CMD 2 /* Modes & Features */
#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
#define PCI_EXP_DEVCTL 8 /* Device Control */
#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */ #define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */ #define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */ #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */

7
src/include/ipxe/pci.h
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@@ -104,6 +104,10 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
#define PCI_PM_CTRL_PME_ENABLE 0x0100 /**< PME pin enable */ #define PCI_PM_CTRL_PME_ENABLE 0x0100 /**< PME pin enable */
#define PCI_PM_CTRL_PME_STATUS 0x8000 /**< PME pin status */ #define PCI_PM_CTRL_PME_STATUS 0x8000 /**< PME pin status */
/** PCI Express */
#define PCI_EXP_DEVCTL 0x08
#define PCI_EXP_DEVCTL_FLR 0x8000 /**< Function level reset */
/** Uncorrectable error status */ /** Uncorrectable error status */
#define PCI_ERR_UNCOR_STATUS 0x04 #define PCI_ERR_UNCOR_STATUS 0x04
@@ -128,6 +132,9 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
( ( ( (base) & 0xff ) << 16 ) | ( ( (sub) & 0xff ) << 8 ) | \ ( ( ( (base) & 0xff ) << 16 ) | ( ( (sub) & 0xff ) << 8 ) | \
( ( (progif) & 0xff) << 0 ) ) ( ( (progif) & 0xff) << 0 ) )
/** PCI Express function level reset delay (in ms) */
#define PCI_EXP_FLR_DELAY_MS 100
/** A PCI device ID list entry */ /** A PCI device ID list entry */
struct pci_device_id { struct pci_device_id {
/** Name */ /** Name */