mirror of
https://github.com/ipxe/ipxe
synced 2025-12-22 21:11:03 +03:00
[pci] Rewrite unrelicensable portions of pci.h
Signed-off-by: Michael Brown <mcb30@ipxe.org>
This commit is contained in:
@@ -62,8 +62,8 @@ static unsigned long pci_bar ( struct pci_device *pci, unsigned int reg ) {
|
||||
uint32_t high;
|
||||
|
||||
pci_read_config_dword ( pci, reg, &low );
|
||||
if ( ( low & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK) )
|
||||
== (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64) ){
|
||||
if ( ( low & (PCI_BASE_ADDRESS_SPACE_IO|PCI_BASE_ADDRESS_MEM_TYPE_MASK))
|
||||
== PCI_BASE_ADDRESS_MEM_TYPE_64 ) {
|
||||
pci_read_config_dword ( pci, reg + 4, &high );
|
||||
if ( high ) {
|
||||
if ( sizeof ( unsigned long ) > sizeof ( uint32_t ) ) {
|
||||
@@ -97,10 +97,10 @@ unsigned long pci_bar_start ( struct pci_device *pci, unsigned int reg ) {
|
||||
unsigned long bar;
|
||||
|
||||
bar = pci_bar ( pci, reg );
|
||||
if ( (bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY ){
|
||||
return ( bar & PCI_BASE_ADDRESS_MEM_MASK );
|
||||
if ( bar & PCI_BASE_ADDRESS_SPACE_IO ) {
|
||||
return ( bar & ~PCI_BASE_ADDRESS_IO_MASK );
|
||||
} else {
|
||||
return ( bar & PCI_BASE_ADDRESS_IO_MASK );
|
||||
return ( bar & ~PCI_BASE_ADDRESS_MEM_MASK );
|
||||
}
|
||||
}
|
||||
|
||||
@@ -126,11 +126,11 @@ static void pci_read_bases ( struct pci_device *pci ) {
|
||||
if ( bar & PCI_BASE_ADDRESS_SPACE_IO ) {
|
||||
if ( ! pci->ioaddr )
|
||||
pci->ioaddr =
|
||||
( bar & PCI_BASE_ADDRESS_IO_MASK );
|
||||
( bar & ~PCI_BASE_ADDRESS_IO_MASK );
|
||||
} else {
|
||||
if ( ! pci->membase )
|
||||
pci->membase =
|
||||
( bar & PCI_BASE_ADDRESS_MEM_MASK );
|
||||
( bar & ~PCI_BASE_ADDRESS_MEM_MASK );
|
||||
/* Skip next BAR if 64-bit */
|
||||
if ( bar & PCI_BASE_ADDRESS_MEM_TYPE_64 )
|
||||
reg += 4;
|
||||
@@ -185,7 +185,7 @@ int pci_read_config ( struct pci_device *pci ) {
|
||||
pci->busdevfn = PCI_FIRST_FUNC ( pci->busdevfn );
|
||||
pci_read_config_byte ( pci, PCI_HEADER_TYPE, &hdrtype );
|
||||
pci->busdevfn = busdevfn;
|
||||
if ( ! ( hdrtype & 0x80 ) )
|
||||
if ( ! ( hdrtype & PCI_HEADER_TYPE_MULTI ) )
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
|
||||
@@ -26,7 +26,7 @@ int pci_find_capability ( struct pci_device *pci, int cap ) {
|
||||
return 0;
|
||||
|
||||
pci_read_config_byte ( pci, PCI_HEADER_TYPE, &hdr_type );
|
||||
switch ( hdr_type & 0x7F ) {
|
||||
switch ( hdr_type & PCI_HEADER_TYPE_MASK ) {
|
||||
case PCI_HEADER_TYPE_NORMAL:
|
||||
case PCI_HEADER_TYPE_BRIDGE:
|
||||
default:
|
||||
@@ -38,13 +38,13 @@ int pci_find_capability ( struct pci_device *pci, int cap ) {
|
||||
}
|
||||
while ( ttl-- && pos >= 0x40 ) {
|
||||
pos &= ~3;
|
||||
pci_read_config_byte ( pci, pos + PCI_CAP_LIST_ID, &id );
|
||||
pci_read_config_byte ( pci, pos + PCI_CAP_ID, &id );
|
||||
DBG ( "PCI Capability: %d\n", id );
|
||||
if ( id == 0xff )
|
||||
break;
|
||||
if ( id == cap )
|
||||
return pos;
|
||||
pci_read_config_byte ( pci, pos + PCI_CAP_LIST_NEXT, &pos );
|
||||
pci_read_config_byte ( pci, pos + PCI_CAP_NEXT, &pos );
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
@@ -76,9 +76,9 @@ unsigned long pci_bar_size ( struct pci_device *pci, unsigned int reg ) {
|
||||
/* Restore the original command register. This reenables decoding. */
|
||||
pci_write_config_word ( pci, PCI_COMMAND, cmd );
|
||||
if ( start & PCI_BASE_ADDRESS_SPACE_IO ) {
|
||||
size &= PCI_BASE_ADDRESS_IO_MASK;
|
||||
size &= ~PCI_BASE_ADDRESS_IO_MASK;
|
||||
} else {
|
||||
size &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
size &= ~PCI_BASE_ADDRESS_MEM_MASK;
|
||||
}
|
||||
/* Find the lowest bit set */
|
||||
size = size & ~( size - 1 );
|
||||
|
||||
Reference in New Issue
Block a user