sysadmin/ipxe
1
0
Fork 0
mirror of https://github.com/ipxe/ipxe synced 2025-12-17 10:01:03 +03:00
Code Issues Packages Projects Releases Wiki Activity

[dwmac] Add driver for DesignWare Ethernet MAC

Browse Source 
Add a basic driver for the DesignWare Ethernet MAC network interface
as found in the Lichee Pi 4A.

Signed-off-by: Michael Brown <mcb30@ipxe.org>
This commit is contained in:
Michael Brown
2025-07-10 13:44:37 +01:00
parent bbabde8ff8
commit c2cdc1d31e
3 changed files with 895 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

656
src/drivers/net/dwmac.c Normal file
View File

@@ -0,0 +1,656 @@
/*
* Copyright (C) 2025 Michael Brown <mbrown@fensystems.co.uk>.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
* You can also choose to distribute this program under the terms of
* the Unmodified Binary Distribution Licence (as given in the file
* COPYING.UBDL), provided that you have satisfied its requirements.
*/
FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
#include <stdint.h>
#include <string.h>
#include <errno.h>
#include <byteswap.h>
#include <ipxe/netdevice.h>
#include <ipxe/ethernet.h>
#include <ipxe/if_ether.h>
#include <ipxe/iobuf.h>
#include <ipxe/timer.h>
#include <ipxe/devtree.h>
#include <ipxe/fdt.h>
#include "dwmac.h"
/** @file
*
* Synopsys DesignWare MAC network driver
*
*/
/******************************************************************************
*
* Debug
*
******************************************************************************
*/
/**
* Dump MAC registers (for debugging)
*
* @v dwmac DesignWare MAC device
*/
static void dwmac_dump_mac ( struct dwmac *dwmac ) {
/* Do nothing unless debugging is enabled */
if ( ! DBG_LOG )
return;
/* Dump MAC registers */
DBGC ( dwmac, "DWMAC %s ver %08x cfg %08x flt %08x flo %08x\n",
dwmac->name, readl ( dwmac->regs + DWMAC_VER ),
readl ( dwmac->regs + DWMAC_CFG ),
readl ( dwmac->regs + DWMAC_FILTER ),
readl ( dwmac->regs + DWMAC_FLOW ) );
DBGC ( dwmac, "DWMAC %s isr %08x dbg %08x gmi %08x\n",
dwmac->name, readl ( dwmac->regs + DWMAC_ISR ),
readl ( dwmac->regs + DWMAC_DEBUG ),
readl ( dwmac->regs + DWMAC_GMII ) );
}
/**
* Dump DMA registers (for debugging)
*
* @v dwmac DesignWare MAC device
*/
static void dwmac_dump_dma ( struct dwmac *dwmac ) {
uint32_t status;
/* Do nothing unless debugging is enabled */
if ( ! DBG_LOG )
return;
/* Dump DMA registers */
status = readl ( dwmac->regs + DWMAC_STATUS );
DBGC ( dwmac, "DWMAC %s bus %08x fea %08x axi %08x ahb %08x\n",
dwmac->name, readl ( dwmac->regs + DWMAC_BUS ),
readl ( dwmac->regs + DWMAC_FEATURE ),
readl ( dwmac->regs + DWMAC_AXI ),
readl ( dwmac->regs + DWMAC_AHB ) );
DBGC ( dwmac, "DWMAC %s opm %08x sta %08x drp %08x\n",
dwmac->name, readl ( dwmac->regs + DWMAC_OP ),
status, readl ( dwmac->regs + DWMAC_DROP ) );
DBGC ( dwmac, "DWMAC %s txb %08x txd %08x txb %08x\n",
dwmac->name, readl ( dwmac->regs + DWMAC_TXBASE ),
readl ( dwmac->regs + DWMAC_TXDESC ),
readl ( dwmac->regs + DWMAC_TXBUF ) );
DBGC ( dwmac, "DWMAC %s rxb %08x rxd %08x rxb %08x\n",
dwmac->name, readl ( dwmac->regs + DWMAC_RXBASE ),
readl ( dwmac->regs + DWMAC_RXDESC ),
readl ( dwmac->regs + DWMAC_RXBUF ) );
/* Clear sticky bits in status register, since nothing else will */
writel ( status, ( dwmac->regs + DWMAC_STATUS ) );
}
/**
* Dump all registers (for debugging)
*
* @v dwmac DesignWare MAC device
*/
static void __attribute__ (( unused )) dwmac_dump ( struct dwmac *dwmac ) {
/* Dump MAC and DMA registers */
dwmac_dump_mac ( dwmac );
dwmac_dump_dma ( dwmac );
}
/******************************************************************************
*
* Device reset
*
******************************************************************************
*/
/**
* Reset hardware
*
* @v dwmac DesignWare MAC device
* @ret rc Return status code
*/
static int dwmac_reset ( struct dwmac *dwmac ) {
unsigned int i;
uint32_t bus;
/* Trigger software reset */
writel ( DWMAC_BUS_SWR, ( dwmac->regs + DWMAC_BUS ) );
/* Wait for reset to complete */
for ( i = 0 ; i < DWMAC_RESET_MAX_WAIT_MS ; i++ ) {
/* Delay */
mdelay ( 1 );
/* Check for reset completion */
bus = readl ( dwmac->regs + DWMAC_BUS );
if ( ! ( bus & DWMAC_BUS_SWR ) )
return 0;
}
DBGC ( dwmac, "DWMAC %s timed out waiting for reset\n",
dwmac->name );
return -ETIMEDOUT;
}
/******************************************************************************
*
* Link state
*
******************************************************************************
*/
/**
* Check link state
*
* @v netdev Network device
*/
static void dwmac_check_link ( struct net_device *netdev ) {
struct dwmac *dwmac = netdev->priv;
uint32_t gmii;
/* Read SGMII/RGMII link status */
gmii = readl ( dwmac->regs + DWMAC_GMII );
DBGC ( dwmac, "DWMAC %s GMII link status %#08x\n", dwmac->name, gmii );
/* Update network device */
if ( gmii & DWMAC_GMII_LINK ) {
netdev_link_up ( netdev );
} else {
netdev_link_down ( netdev );
}
}
/******************************************************************************
*
* Network device interface
*
******************************************************************************
*/
/**
* Create descriptor ring
*
* @v dwmac DesignWare MAC device
* @v ring Descriptor ring
* @ret rc Return status code
*/
static int dwmac_create_ring ( struct dwmac *dwmac, struct dwmac_ring *ring ) {
struct dwmac_descriptor *desc;
struct dwmac_descriptor *next;
physaddr_t base;
unsigned int i;
/* Allocate descriptor ring (on its own size) */
ring->desc = dma_alloc ( dwmac->dma, &ring->map, ring->len, ring->len );
if ( ! ring->desc )
return -ENOMEM;
/* Initialise descriptor ring */
memset ( ring->desc, 0, ring->len );
for ( i = 0 ; i < ring->count ; i++ ) {
desc = &ring->desc[i];
desc->size = cpu_to_le16 ( DWMAC_RX_LEN |
DWMAC_SIZE_RX_CHAIN );
desc->ctrl = ring->ctrl;
assert ( desc->ctrl & DWMAC_CTRL_CHAIN );
next = &ring->desc[ ( i + 1 ) & ( ring->count - 1 ) ];
desc->next = dma ( &ring->map, next );
}
wmb();
/* Program ring address */
base = dma ( &ring->map, ring->desc );
assert ( base == ( ( uint32_t ) base ) );
writel ( base, ( dwmac->regs + DWMAC_DMA + ring->qbase ) );
DBGC ( dwmac, "DWMAC %s ring %02x is at [%08lx,%08lx)\n",
dwmac->name, ring->qbase, virt_to_phys ( ring->desc ),
( virt_to_phys ( ring->desc ) + ring->len ) );
return 0;
}
/**
* Destroy descriptor ring
*
* @v dwmac DesignWare MAC device
* @v ring Descriptor ring
*/
static void dwmac_destroy_ring ( struct dwmac *dwmac,
struct dwmac_ring *ring ) {
/* Clear ring address */
writel ( 0, ( dwmac->regs + DWMAC_DMA + ring->qbase ) );
/* Free descriptor ring */
dma_free ( &ring->map, ring->desc, ring->len );
ring->desc = NULL;
ring->prod = 0;
ring->cons = 0;
}
/**
* Refill receive descriptor ring
*
* @v dwmac DesignWare MAC device
*/
static void dwmac_refill_rx ( struct dwmac *dwmac ) {
struct dwmac_descriptor *rx;
struct io_buffer *iobuf;
unsigned int rx_idx;
unsigned int refilled = 0;
/* Refill ring */
while ( ( dwmac->rx.prod - dwmac->rx.cons ) != DWMAC_NUM_RX_DESC ) {
/* Allocate I/O buffer */
iobuf = alloc_rx_iob ( DWMAC_RX_LEN, dwmac->dma );
if ( ! iobuf ) {
/* Wait for next refill */
break;
}
/* Get next receive descriptor */
rx_idx = ( dwmac->rx.prod++ % DWMAC_NUM_RX_DESC );
rx = &dwmac->rx.desc[rx_idx];
/* Populate receive descriptor */
rx->addr = cpu_to_le32 ( iob_dma ( iobuf ) );
wmb();
rx->stat = cpu_to_le32 ( DWMAC_STAT_OWN );
/* Record I/O buffer */
assert ( dwmac->rx_iobuf[rx_idx] == NULL );
dwmac->rx_iobuf[rx_idx] = iobuf;
DBGC2 ( dwmac, "DWMAC %s RX %d is [%08lx,%08lx)\n",
dwmac->name, rx_idx, virt_to_phys ( iobuf->data ),
( virt_to_phys ( iobuf->data ) + DWMAC_RX_LEN ) );
refilled++;
}
/* Trigger poll */
if ( refilled ) {
wmb();
writel ( 0, ( dwmac->regs + DWMAC_RXPOLL ) );
}
}
/**
* Open network device
*
* @v netdev Network device
* @ret rc Return status code
*/
static int dwmac_open ( struct net_device *netdev ) {
struct dwmac *dwmac = netdev->priv;
union dwmac_mac mac;
int rc;
/* Create transmit descriptor ring */
if ( ( rc = dwmac_create_ring ( dwmac, &dwmac->tx ) ) != 0 )
goto err_create_tx;
/* Create receive descriptor ring */
if ( ( rc = dwmac_create_ring ( dwmac, &dwmac->rx ) ) != 0 )
goto err_create_rx;
/* Set MAC address */
memcpy ( mac.raw, netdev->ll_addr, ETH_ALEN );
writel ( mac.reg.addrl, ( dwmac->regs + DWMAC_ADDRL ) );
writel ( mac.reg.addrh, ( dwmac->regs + DWMAC_ADDRH ) );
/* Enable promiscuous mode */
writel ( DWMAC_FILTER_PR, ( dwmac->regs + DWMAC_FILTER ) );
/* Enable transmit and receive */
writel ( ( DWMAC_OP_TXSF | DWMAC_OP_RXSF |
DWMAC_OP_TXEN | DWMAC_OP_RXEN ),
( dwmac->regs + DWMAC_OP ) );
writel ( ( DWMAC_CFG_DO | DWMAC_CFG_FD |
DWMAC_CFG_TXEN | DWMAC_CFG_RXEN ),
( dwmac->regs + DWMAC_CFG ) );
/* Refill receive descriptor ring */
dwmac_refill_rx ( dwmac );
/* Update link state */
dwmac_check_link ( netdev );
return 0;
dwmac_destroy_ring ( dwmac, &dwmac->rx );
err_create_rx:
dwmac_destroy_ring ( dwmac, &dwmac->tx );
err_create_tx:
return rc;
}
/**
* Close network device
*
* @v netdev Network device
*/
static void dwmac_close ( struct net_device *netdev ) {
struct dwmac *dwmac = netdev->priv;
unsigned int i;
/* Reset NIC */
dwmac_reset ( dwmac );
/* Discard unused receive buffers */
for ( i = 0 ; i < DWMAC_NUM_RX_DESC ; i++ ) {
if ( dwmac->rx_iobuf[i] )
free_rx_iob ( dwmac->rx_iobuf[i] );
dwmac->rx_iobuf[i] = NULL;
}
/* Destroy receive descriptor ring */
dwmac_destroy_ring ( dwmac, &dwmac->rx );
/* Destroy transmit descriptor ring */
dwmac_destroy_ring ( dwmac, &dwmac->tx );
}
/**
* Transmit packet
*
* @v netdev Network device
* @v iobuf I/O buffer
* @ret rc Return status code
*/
static int dwmac_transmit ( struct net_device *netdev,
struct io_buffer *iobuf ) {
struct dwmac *dwmac = netdev->priv;
struct dwmac_descriptor *tx;
unsigned int tx_idx;
/* Get next transmit descriptor */
if ( ( dwmac->tx.prod - dwmac->tx.cons ) >= DWMAC_NUM_TX_DESC ) {
DBGC ( dwmac, "DWMAC %s out of transmit descriptors\n",
dwmac->name );
return -ENOBUFS;
}
tx_idx = ( dwmac->tx.prod % DWMAC_NUM_TX_DESC );
tx = &dwmac->tx.desc[tx_idx];
/* Update producer index */
dwmac->tx.prod++;
/* Populate transmit descriptor */
tx->size = cpu_to_le16 ( iob_len ( iobuf ) );
tx->addr = cpu_to_le32 ( iob_dma ( iobuf ) );
wmb();
tx->stat = cpu_to_le32 ( DWMAC_STAT_OWN | DWMAC_STAT_TX_LAST |
DWMAC_STAT_TX_FIRST | DWMAC_STAT_TX_CHAIN );
wmb();
/* Initiate transmission */
writel ( 0, ( dwmac->regs + DWMAC_TXPOLL ) );
DBGC2 ( dwmac, "DWMAC %s TX %d is [%08lx,%08lx)\n",
dwmac->name, tx_idx, virt_to_phys ( iobuf->data ),
( virt_to_phys ( iobuf->data ) + iob_len ( iobuf ) ) );
return 0;
}
/**
* Poll for completed packets
*
* @V netdev Network device
*/
static void dwmac_poll_tx ( struct net_device *netdev ) {
struct dwmac *dwmac = netdev->priv;
struct dwmac_descriptor *tx;
unsigned int tx_idx;
/* Check for completed packets */
while ( dwmac->tx.cons != dwmac->tx.prod ) {
/* Get next transmit descriptor */
tx_idx = ( dwmac->tx.cons % DWMAC_NUM_TX_DESC );
tx = &dwmac->tx.desc[tx_idx];
/* Stop if descriptor is still owned by hardware */
if ( tx->stat & cpu_to_le32 ( DWMAC_STAT_OWN ) )
return;
dwmac->tx.cons++;
/* Report completion */
if ( tx->stat & cpu_to_le32 ( DWMAC_STAT_ERR ) ) {
DBGC ( dwmac, "DWMAC %s TX %d error %#08x\n",
dwmac->name, tx_idx, le32_to_cpu ( tx->stat ) );
dwmac_dump ( dwmac );
netdev_tx_complete_next_err ( netdev, -EIO );
} else {
DBGC2 ( dwmac, "DWMAC %s TX %d complete\n",
dwmac->name, tx_idx );
netdev_tx_complete_next ( netdev );
}
}
}
/**
* Poll for received packets
*
* @v netdev Network device
*/
static void dwmac_poll_rx ( struct net_device *netdev ) {
struct dwmac *dwmac = netdev->priv;
struct dwmac_descriptor *rx;
struct io_buffer *iobuf;
unsigned int rx_idx;
uint32_t stat;
size_t len;
/* Check for received packets */
while ( dwmac->rx.cons != dwmac->rx.prod ) {
/* Get next receive descriptor */
rx_idx = ( dwmac->rx.cons % DWMAC_NUM_RX_DESC );
rx = &dwmac->rx.desc[rx_idx];
/* Stop if descriptor is still in use */
if ( rx->stat & cpu_to_le32 ( DWMAC_STAT_OWN ) )
return;
dwmac->rx.cons++;
/* Consume I/O buffer */
iobuf = dwmac->rx_iobuf[rx_idx];
assert ( iobuf != NULL );
dwmac->rx_iobuf[rx_idx] = NULL;
/* Hand off to network stack */
stat = le32_to_cpu ( rx->stat );
assert ( stat & DWMAC_STAT_RX_FIRST );
assert ( stat & DWMAC_STAT_RX_LAST );
if ( stat & DWMAC_STAT_ERR ) {
DBGC ( dwmac, "DWMAC %s RX %d error %#08x\n",
dwmac->name, rx_idx, stat );
dwmac_dump ( dwmac );
netdev_rx_err ( netdev, iobuf, -EIO );
} else {
len = ( DWMAC_STAT_RX_LEN ( stat ) - 4 /* CRC */ );
iob_put ( iobuf, len );
DBGC2 ( dwmac, "DWMAC %s RX %d complete (length "
"%zd)\n", dwmac->name, rx_idx, len );
netdev_rx ( netdev, iobuf );
}
}
}
/**
* Poll for completed and received packets
*
* @v netdev Network device
*/
static void dwmac_poll ( struct net_device *netdev ) {
struct dwmac *dwmac = netdev->priv;
uint32_t status;
/* Check for link status changes */
status = readl ( dwmac->regs + DWMAC_STATUS );
if ( status & DWMAC_STATUS_LINK )
dwmac_check_link ( netdev );
/* Poll for TX competions, if applicable */
dwmac_poll_tx ( netdev );
/* Poll for RX completions */
dwmac_poll_rx ( netdev );
/* Refill RX ring */
dwmac_refill_rx ( dwmac );
}
/** DesignWare MAC network device operations */
static struct net_device_operations dwmac_operations = {
.open = dwmac_open,
.close = dwmac_close,
.transmit = dwmac_transmit,
.poll = dwmac_poll,
};
/******************************************************************************
*
* Devicetree interface
*
******************************************************************************
*/
/**
* Probe devicetree device
*
* @v dt Devicetree device
* @v offset Starting node offset
* @ret rc Return status code
*/
static int dwmac_probe ( struct dt_device *dt, unsigned int offset ) {
struct net_device *netdev;
struct dwmac *dwmac;
union dwmac_mac mac;
int rc;
/* Allocate and initialise net device */
netdev = alloc_etherdev ( sizeof ( *dwmac ) );
if ( ! netdev ) {
rc = -ENOMEM;
goto err_alloc;
}
netdev_init ( netdev, &dwmac_operations );
dwmac = netdev->priv;
dt_set_drvdata ( dt, netdev );
netdev->dev = &dt->dev;
netdev->dma = &dt->dma;
memset ( dwmac, 0, sizeof ( *dwmac ) );
dwmac->dma = &dt->dma;
dwmac->name = netdev->dev->name;
dwmac_init_ring ( &dwmac->tx, DWMAC_NUM_TX_DESC, DWMAC_TXBASE,
( DWMAC_CTRL_TX_FIRST | DWMAC_CTRL_TX_LAST |
DWMAC_CTRL_CHAIN ) );
dwmac_init_ring ( &dwmac->rx, DWMAC_NUM_RX_DESC, DWMAC_RXBASE,
DWMAC_CTRL_CHAIN );
/* Map registers */
dwmac->regs = dt_ioremap ( dt, offset, DWMAC_REG_IDX, DWMAC_REG_LEN );
if ( ! dwmac->regs ) {
rc = -ENODEV;
goto err_ioremap;
}
/* Fetch devicetree MAC address */
if ( ( rc = fdt_mac ( &sysfdt, offset, netdev ) ) != 0 ) {
DBGC ( dwmac, "DWMAC %s could not fetch MAC: %s\n",
dwmac->name, strerror ( rc ) );
goto err_mac;
}
/* Fetch current MAC address, if set */
mac.reg.addrl = readl ( dwmac->regs + DWMAC_ADDRL );
mac.reg.addrh = readl ( dwmac->regs + DWMAC_ADDRH );
memcpy ( netdev->ll_addr, mac.raw, ETH_ALEN );
/* Reset the NIC */
if ( ( rc = dwmac_reset ( dwmac ) ) != 0 )
goto err_reset;
/* Register network device */
if ( ( rc = register_netdev ( netdev ) ) != 0 )
goto err_register_netdev;
/* Update link state */
dwmac_check_link ( netdev );
return 0;
unregister_netdev ( netdev );
err_register_netdev:
dwmac_reset ( dwmac );
err_reset:
err_mac:
iounmap ( dwmac->regs );
err_ioremap:
netdev_nullify ( netdev );
netdev_put ( netdev );
err_alloc:
return rc;
}
/**
* Remove devicetree device
*
* @v dt Devicetree device
*/
static void dwmac_remove ( struct dt_device *dt ) {
struct net_device *netdev = dt_get_drvdata ( dt );
struct dwmac *dwmac = netdev->priv;
/* Unregister network device */
unregister_netdev ( netdev );
/* Reset card */
dwmac_reset ( dwmac );
/* Free network device */
iounmap ( dwmac->regs );
netdev_nullify ( netdev );
netdev_put ( netdev );
}
/** DesignWare MAC compatible model identifiers */
static const char * dwmac_ids[] = {
"thead,light-dwmac",
"snps,dwmac",
};
/** DesignWare MAC devicetree driver */
struct dt_driver dwmac_driver __dt_driver = {
.name = "dwmac",
.ids = dwmac_ids,
.id_count = ( sizeof ( dwmac_ids ) / sizeof ( dwmac_ids[0] ) ),
.probe = dwmac_probe,
.remove = dwmac_remove,
};

238
src/drivers/net/dwmac.h Normal file
View File

@@ -0,0 +1,238 @@
#ifndef _DWMAC_H
#define _DWMAC_H
/** @file
*
* Synopsys DesignWare MAC network driver
*
*/
FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
#include <stdint.h>
#include <ipxe/if_ether.h>
/** I/O region index */
#define DWMAC_REG_IDX 0
/** I/O region length */
#define DWMAC_REG_LEN 0x2000
/** MAC register block */
#define DWMAC_MAC 0x0000
#define DWMAC_MAC_REG( n ) ( DWMAC_MAC + ( (n) * 4 ) )
/** MAC configuration register */
#define DWMAC_CFG DWMAC_MAC_REG ( 0 )
#define DWMAC_CFG_DO 0x00002000 /**< Disable RX own frames */
#define DWMAC_CFG_FD 0x00000800 /**< Full duplex */
#define DWMAC_CFG_TXEN 0x00000008 /**< TX enabled */
#define DWMAC_CFG_RXEN 0x00000004 /**< RX enabled */
/** MAC filter register */
#define DWMAC_FILTER DWMAC_MAC_REG ( 1 )
#define DWMAC_FILTER_PR 0x00000001 /**< Promiscuous mode */
/** Flow control register */
#define DWMAC_FLOW DWMAC_MAC_REG ( 6 )
/** Version register */
#define DWMAC_VER DWMAC_MAC_REG ( 8 )
/** Debug register */
#define DWMAC_DEBUG DWMAC_MAC_REG ( 9 )
/** Interrupt status register */
#define DWMAC_ISR DWMAC_MAC_REG ( 14 )
/** MAC address high register */
#define DWMAC_ADDRH DWMAC_MAC_REG ( 16 )
/** MAC address low register */
#define DWMAC_ADDRL DWMAC_MAC_REG ( 17 )
/** A DesignWare MAC address */
union dwmac_mac {
struct {
uint32_t addrl;
uint32_t addrh;
} __attribute__ (( packed )) reg;
uint8_t raw[ETH_ALEN];
};
/** SGMII/RGMII status register */
#define DWMAC_GMII DWMAC_MAC_REG ( 54 )
#define DWMAC_GMII_LINK 0x00000008 /**< Link up */
/** DMA register block */
#define DWMAC_DMA 0x1000
#define DWMAC_DMA_REG( n ) ( DWMAC_DMA + ( (n) * 4 ) )
/** Bus mode register */
#define DWMAC_BUS DWMAC_DMA_REG ( 0 )
#define DWMAC_BUS_PBL4 0x01000000 /**< 4x PBL mode */
#define DWMAC_BUS_USP 0x00800000 /**< Use separate PBL */
#define DWMAC_BUS_RPBL(x) ( (x) << 17 ) /**< RX DMA PBL */
#define DWMAC_BUS_FB 0x00010000 /**< Fixed burst */
#define DWMAC_BUS_PBL(x) ( (x) << 8 ) /**< (TX) DMA PBL */
#define DWMAC_BUS_SWR 0x00000001 /**< Software reset */
/** Time to wait for software reset to complete */
#define DWMAC_RESET_MAX_WAIT_MS 500
/** Transmit poll demand register */
#define DWMAC_TXPOLL DWMAC_DMA_REG ( 1 )
/** Receive poll demand register */
#define DWMAC_RXPOLL DWMAC_DMA_REG ( 2 )
/** Receive descriptor list address register */
#define DWMAC_RXBASE DWMAC_DMA_REG ( 3 )
/** Transmit descriptor list address register */
#define DWMAC_TXBASE DWMAC_DMA_REG ( 4 )
/** Status register */
#define DWMAC_STATUS DWMAC_DMA_REG ( 5 )
#define DWMAC_STATUS_LINK 0x04000000 /**< Link status change */
/** Operation mode register */
#define DWMAC_OP DWMAC_DMA_REG ( 6 )
#define DWMAC_OP_RXSF 0x02000000 /**< RX store and forward */
#define DWMAC_OP_TXSF 0x00200000 /**< TX store and forward */
#define DWMAC_OP_TXEN 0x00002000 /**< TX enabled */
#define DWMAC_OP_RXEN 0x00000002 /**< RX enabled */
/** Packet drop counter register */
#define DWMAC_DROP DWMAC_DMA_REG ( 8 )
/** AXI bus mode register */
#define DWMAC_AXI DWMAC_DMA_REG ( 10 )
/** AHB or AXI status register */
#define DWMAC_AHB DWMAC_DMA_REG ( 11 )
/** Current transmit descriptor register */
#define DWMAC_TXDESC DWMAC_DMA_REG ( 18 )
/** Current receive descriptor register */
#define DWMAC_RXDESC DWMAC_DMA_REG ( 19 )
/** Current transmit buffer address register */
#define DWMAC_TXBUF DWMAC_DMA_REG ( 20 )
/** Current receive buffer address register */
#define DWMAC_RXBUF DWMAC_DMA_REG ( 21 )
/** Hardware feature register */
#define DWMAC_FEATURE DWMAC_DMA_REG ( 22 )
/** A frame descriptor
*
* We populate the descriptor with values that are valid for both
* normal and enhanced descriptor formats, to avoid needing to care
* about which version of the hardware we have.
*/
struct dwmac_descriptor {
/** Completion status */
uint32_t stat;
/** Buffer size */
uint16_t size;
/** Reserved */
uint8_t reserved_a;
/** Ring control */
uint8_t ctrl;
/** Buffer address */
uint32_t addr;
/** Next descriptor address */
uint32_t next;
} __attribute__ (( packed ));
/* Completion status */
#define DWMAC_STAT_OWN 0x80000000 /**< Owned by hardware */
#define DWMAC_STAT_TX_LAST 0x20000000 /**< Last segment (TX) */
#define DWMAC_STAT_TX_FIRST 0x10000000 /**< First segment (TX) */
#define DWMAC_STAT_TX_CHAIN 0x00100000 /**< Chained descriptor (TX) */
#define DWMAC_STAT_ERR 0x00008000 /**< Error summary */
#define DWMAC_STAT_RX_FIRST 0x00000200 /**< First segment (RX) */
#define DWMAC_STAT_RX_LAST 0x00000100 /**< Last segment (RX) */
#define DWMAC_STAT_RX_LEN(x) \
( ( (x) >> 16 ) & 0x3fff ) /**< Frame length (RX) */
/** Buffer size */
#define DWMAC_SIZE_RX_CHAIN 0x4000 /**< Chained descriptor (RX) */
/* Ring control */
#define DWMAC_CTRL_TX_LAST 0x40 /**< Last segment (TX) */
#define DWMAC_CTRL_TX_FIRST 0x20 /**< First segment (TX) */
#define DWMAC_CTRL_CHAIN 0x01 /**< Chained descriptor */
/** A DesignWare descriptor ring */
struct dwmac_ring {
/** Descriptors */
struct dwmac_descriptor *desc;
/** Descriptor ring DMA mapping */
struct dma_mapping map;
/** Producer index */
unsigned int prod;
/** Consumer index */
unsigned int cons;
/** Queue base address register (within DMA block) */
uint8_t qbase;
/** Number of descriptors */
uint8_t count;
/** Default control flags */
uint8_t ctrl;
/** Length of descriptors */
size_t len;
};
/** Number of transmit descriptors */
#define DWMAC_NUM_TX_DESC 16
/** Number of receive descriptors */
#define DWMAC_NUM_RX_DESC 16
/** Length of receive buffers
*
* Must be a multiple of 16.
*/
#define DWMAC_RX_LEN 1536
/**
* Initialise descriptor ring
*
* @v ring Descriptor ring
* @v count Number of descriptors
* @v qbase Queue base address register
* @v ctrl Default descriptor control flags
*/
static inline __attribute__ (( always_inline )) void
dwmac_init_ring ( struct dwmac_ring *ring, unsigned int count,
unsigned int qbase, unsigned int ctrl ) {
ring->qbase = ( qbase - DWMAC_DMA );
ring->count = count;
ring->ctrl = ctrl;
ring->len = ( count * sizeof ( ring->desc[0] ) );
}
/** A DesignWare MAC network card */
struct dwmac {
/** Registers */
void *regs;
/** DMA device */
struct dma_device *dma;
/** Device name (for debugging) */
const char *name;
/** Transmit ring */
struct dwmac_ring tx;
/** Receive ring */
struct dwmac_ring rx;
/** Receive I/O buffers */
struct io_buffer *rx_iobuf[DWMAC_NUM_RX_DESC];
};
#endif /* _DWMAC_H */

1
src/include/ipxe/errfile.h
View File

@@ -235,6 +235,7 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
#define ERRFILE_atl2_hw ( ERRFILE_DRIVER | 0x00d90000 )
#define ERRFILE_devtree ( ERRFILE_DRIVER | 0x00da0000 )
#define ERRFILE_cgem ( ERRFILE_DRIVER | 0x00db0000 )
#define ERRFILE_dwmac ( ERRFILE_DRIVER | 0x00dc0000 )
#define ERRFILE_aoe ( ERRFILE_NET | 0x00000000 )
#define ERRFILE_arp ( ERRFILE_NET | 0x00010000 )