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https://github.com/ipxe/ipxe
synced 2026-06-29 00:07:28 +03:00
[build] Fix building for big-endian targets
Fix build errors that arise when building for a big-endian target such as s390x. (Runtime endianness errors may remain: this fixes only those errors that are detected at build time.) Signed-off-by: Michael Brown <mcb30@ipxe.org>
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@@ -82,7 +82,7 @@ static int pcibridge_probe ( struct pci_device *pci ) {
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/* Read bus configuration */
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pci_read_config_dword ( pci, PCI_PRIMARY, &bridge->buses );
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cpu_to_le32s ( &buses );
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cpu_to_le32s ( &bridge->buses );
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/* Read memory base and limit */
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pci_read_config_word ( pci, PCI_MEM_BASE, &base );
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@@ -380,7 +380,7 @@ epic100_poll(struct nic *nic, int retrieve)
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unsigned long status;
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entry = cur_rx % RX_RING_SIZE;
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if ((rx_ring[entry].status & cpu_to_le32(RRING_OWN)) == RRING_OWN)
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if (rx_ring[entry].status & cpu_to_le32(RRING_OWN))
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return (0);
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if ( ! retrieve ) return 1;
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@@ -739,17 +739,16 @@ __vxge_hw_legacy_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg)
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enum vxge_hw_status
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__vxge_hw_vpath_swapper_set(struct vxge_hw_vpath_reg __iomem *vpath_reg)
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{
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u64 val64;
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vxge_trace();
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#if (__BYTE_ORDER != __BIG_ENDIAN)
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u64 val64;
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val64 = readq(&vpath_reg->vpath_general_cfg1);
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wmb();
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val64 |= VXGE_HW_VPATH_GENERAL_CFG1_CTL_BYTE_SWAPEN;
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writeq(val64, &vpath_reg->vpath_general_cfg1);
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wmb();
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#endif
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if (__BYTE_ORDER != __BIG_ENDIAN) {
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val64 = readq(&vpath_reg->vpath_general_cfg1);
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wmb();
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val64 |= VXGE_HW_VPATH_GENERAL_CFG1_CTL_BYTE_SWAPEN;
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writeq(val64, &vpath_reg->vpath_general_cfg1);
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wmb();
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}
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return VXGE_HW_OK;
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}
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@@ -1372,10 +1371,9 @@ __vxge_hw_vpath_kdfc_configure(struct __vxge_hw_device *hldev, u32 vp_id)
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val64 |= VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(
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VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY) |
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#if (__BYTE_ORDER != __BIG_ENDIAN)
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VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN |
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#endif
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VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0);
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if (__BYTE_ORDER != __BIG_ENDIAN)
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val64 |= VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN;
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writeq(val64, &vp_reg->kdfc_trpl_fifo_0_ctrl);
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writeq((u64)0, &vp_reg->kdfc_trpl_fifo_0_wb_address);
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@@ -849,7 +849,7 @@ static inline size_t ieee80211_rsn_size ( int npair, int nauth, int npmkid,
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/** Make OUI plus type byte into 32-bit integer for easy comparison */
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#if __BYTE_ORDER == __BIG_ENDIAN
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#define _MKOUI( a, b, c, t ) \
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( ( ( a ) << 24 ) | ( ( b ) << 16 ) | ( ( c ) << 8 ) | ( d ) )
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( ( ( a ) << 24 ) | ( ( b ) << 16 ) | ( ( c ) << 8 ) | ( t ) )
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#define OUI_ORG_MASK 0xFFFFFF00
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#define OUI_TYPE_MASK 0x000000FF
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#else
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