sysadmin/ipxe
1
0
Fork 0
mirror of https://github.com/ipxe/ipxe synced 2026-06-29 00:07:28 +03:00
Code Issues Packages Projects Releases Wiki Activity

[build] Fix building for big-endian targets

Browse Source 
Fix build errors that arise when building for a big-endian target such
as s390x.  (Runtime endianness errors may remain: this fixes only
those errors that are detected at build time.)

Signed-off-by: Michael Brown <mcb30@ipxe.org>
This commit is contained in:
Michael Brown
2026-06-13 16:01:35 +01:00
parent e68ca57f46
commit bfdbd1c4e0
4 changed files with 13 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/drivers/bus/pcibridge.c
+1 -1
View File
@@ -82,7 +82,7 @@ static int pcibridge_probe ( struct pci_device *pci ) {
/* Read bus configuration */ /* Read bus configuration */
pci_read_config_dword ( pci, PCI_PRIMARY, &bridge->buses ); pci_read_config_dword ( pci, PCI_PRIMARY, &bridge->buses );
cpu_to_le32s ( &buses ); cpu_to_le32s ( &bridge->buses );
/* Read memory base and limit */ /* Read memory base and limit */
pci_read_config_word ( pci, PCI_MEM_BASE, &base ); pci_read_config_word ( pci, PCI_MEM_BASE, &base );
src/drivers/net/epic100.c
+1 -1
View File
@@ -380,7 +380,7 @@ epic100_poll(struct nic *nic, int retrieve)
unsigned long status; unsigned long status;
entry = cur_rx % RX_RING_SIZE; entry = cur_rx % RX_RING_SIZE;
if ((rx_ring[entry].status & cpu_to_le32(RRING_OWN)) == RRING_OWN) if (rx_ring[entry].status & cpu_to_le32(RRING_OWN))
return (0); return (0);
if ( ! retrieve ) return 1; if ( ! retrieve ) return 1;
src/drivers/net/vxge/vxge_config.c
+10 -12
View File
@@ -739,17 +739,16 @@ __vxge_hw_legacy_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg)
enum vxge_hw_status enum vxge_hw_status
__vxge_hw_vpath_swapper_set(struct vxge_hw_vpath_reg __iomem *vpath_reg) __vxge_hw_vpath_swapper_set(struct vxge_hw_vpath_reg __iomem *vpath_reg)
{ {
u64 val64;
vxge_trace(); vxge_trace();
#if (__BYTE_ORDER != __BIG_ENDIAN) if (__BYTE_ORDER != __BIG_ENDIAN) {
u64 val64; val64 = readq(&vpath_reg->vpath_general_cfg1);
wmb();
val64 = readq(&vpath_reg->vpath_general_cfg1); val64 |= VXGE_HW_VPATH_GENERAL_CFG1_CTL_BYTE_SWAPEN;
wmb(); writeq(val64, &vpath_reg->vpath_general_cfg1);
val64 |= VXGE_HW_VPATH_GENERAL_CFG1_CTL_BYTE_SWAPEN; wmb();
writeq(val64, &vpath_reg->vpath_general_cfg1); }
wmb();
#endif
return VXGE_HW_OK; return VXGE_HW_OK;
} }
@@ -1372,10 +1371,9 @@ __vxge_hw_vpath_kdfc_configure(struct __vxge_hw_device *hldev, u32 vp_id)
val64 |= VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE( val64 |= VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(
VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY) | VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY) |
#if (__BYTE_ORDER != __BIG_ENDIAN)
VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN |
#endif
VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0); VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0);
if (__BYTE_ORDER != __BIG_ENDIAN)
val64 |= VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN;
writeq(val64, &vp_reg->kdfc_trpl_fifo_0_ctrl); writeq(val64, &vp_reg->kdfc_trpl_fifo_0_ctrl);
writeq((u64)0, &vp_reg->kdfc_trpl_fifo_0_wb_address); writeq((u64)0, &vp_reg->kdfc_trpl_fifo_0_wb_address);
src/include/ipxe/ieee80211.h
+1 -1
View File
@@ -849,7 +849,7 @@ static inline size_t ieee80211_rsn_size ( int npair, int nauth, int npmkid,
/** Make OUI plus type byte into 32-bit integer for easy comparison */ /** Make OUI plus type byte into 32-bit integer for easy comparison */
#if __BYTE_ORDER == __BIG_ENDIAN #if __BYTE_ORDER == __BIG_ENDIAN
#define _MKOUI( a, b, c, t ) \ #define _MKOUI( a, b, c, t ) \
( ( ( a ) << 24 ) | ( ( b ) << 16 ) | ( ( c ) << 8 ) | ( d ) ) ( ( ( a ) << 24 ) | ( ( b ) << 16 ) | ( ( c ) << 8 ) | ( t ) )
#define OUI_ORG_MASK 0xFFFFFF00 #define OUI_ORG_MASK 0xFFFFFF00
#define OUI_TYPE_MASK 0x000000FF #define OUI_TYPE_MASK 0x000000FF
#else #else