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[riscv] Invalidate data cache on completed RX DMA buffers

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The data cache must be invalidated twice for RX DMA buffers: once
before passing ownership to the DMA device (in case the cache happens
to contain dirty data that will be written back at an undefined future
point), and once after receiving ownership from the DMA device (in
case the CPU happens to have speculatively accessed data in the buffer
while it was owned by the hardware).

Only the used portion of the buffer needs to be invalidated after
completion, since we do not care about data within the unused portion.

Update the DMA API to include the used length as an additional
parameter to dma_unmap(), and add the necessary second cache
invalidation pass to the RISC-V DMA API implementation.

Signed-off-by: Michael Brown <mcb30@ipxe.org>
This commit is contained in:
Michael Brown
2025-07-10 14:33:34 +01:00
parent 634d9abefb
commit bbabde8ff8
7 changed files with 65 additions and 27 deletions
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4
src/drivers/net/intelxl.c
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@@ -90,7 +90,7 @@ int intelxl_msix_enable ( struct intelxl_nic *intelxl,
pci_msix_disable ( pci, &intelxl->msix.cap );
err_enable:
dma_unmap ( &intelxl->msix.map );
dma_unmap ( &intelxl->msix.map, sizeof ( intelxl->msix.msg ) );
err_map:
return rc;
}
@@ -112,7 +112,7 @@ void intelxl_msix_disable ( struct intelxl_nic *intelxl,
pci_msix_disable ( pci, &intelxl->msix.cap );
/* Unmap dummy target location */
dma_unmap ( &intelxl->msix.map );
dma_unmap ( &intelxl->msix.map, sizeof ( intelxl->msix.msg ) );
}
/******************************************************************************