[pci] Add support for PCI MSI-X interrupts

The Intel 40 Gigabit Ethernet virtual functions support only MSI-X
interrupts, and will write back completed interrupt descriptors only
when the device attempts to raise an interrupt (or when a complete
cacheline of receive descriptors has been completed).

We cannot actually use MSI-X interrupts within iPXE, since we never
have ownership of the APIC.  However, an MSI-X interrupt is
fundamentally just a DMA write of a single dword to an arbitrary
address.  We can therefore configure the device to "raise" an
interrupt by writing a meaningless value to an otherwise unused memory
location: this is sufficient to trigger the receive descriptor
writeback logic.

Signed-off-by: Michael Brown <mcb30@ipxe.org>

src/include/ipxe/errfile.h

@@ -205,6 +205,7 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
 #define ERRFILE_ena		     ( ERRFILE_DRIVER | 0x00c90000 )
 #define ERRFILE_icplus		     ( ERRFILE_DRIVER | 0x00ca0000 )
 #define ERRFILE_intelxl		     ( ERRFILE_DRIVER | 0x00cb0000 )
+#define ERRFILE_pcimsix		     ( ERRFILE_DRIVER | 0x00cc0000 )
 
 #define ERRFILE_aoe			( ERRFILE_NET | 0x00000000 )
 #define ERRFILE_arp			( ERRFILE_NET | 0x00010000 )

src/include/ipxe/pci.h

@@ -94,6 +94,7 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
 #define PCI_CAP_ID_VPD			0x03	/**< Vital product data */
 #define PCI_CAP_ID_VNDR			0x09	/**< Vendor-specific */
 #define PCI_CAP_ID_EXP			0x10	/**< PCI Express */
+#define PCI_CAP_ID_MSIX			0x11	/**< MSI-X */
 #define PCI_CAP_ID_EA			0x14	/**< Enhanced Allocation */
 
 /** Next capability */
@@ -109,6 +110,16 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
 #define PCI_EXP_DEVCTL		0x08
 #define PCI_EXP_DEVCTL_FLR		0x8000	/**< Function level reset */
 
+/** MSI-X interrupts */
+#define PCI_MSIX_CTRL		0x02
+#define PCI_MSIX_CTRL_ENABLE		0x8000	/**< Enable MSI-X */
+#define PCI_MSIX_CTRL_MASK		0x4000	/**< Mask all interrupts */
+#define PCI_MSIX_CTRL_SIZE(x)	( (x) & 0x07ff ) /**< Table size */
+#define PCI_MSIX_DESC_TABLE	0x04
+#define PCI_MSIX_DESC_PBA	0x08
+#define PCI_MSIX_DESC_BIR(x)	( (x) & 0x00000007 ) /**< BAR index */
+#define PCI_MSIX_DESC_OFFSET(x)	( (x) & 0xfffffff8 ) /**< BAR offset */
+
 /** Uncorrectable error status */
 #define PCI_ERR_UNCOR_STATUS	0x04
 

src/include/ipxe/pcimsix.h

@@ -0,0 +1,77 @@
+#ifndef _IPXE_PCIMSIX_H
+#define _IPXE_PCIMSIX_H
+
+/** @file
+ *
+ * PCI MSI-X interrupts
+ *
+ */
+
+FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
+
+#include <ipxe/pci.h>
+
+/** MSI-X BAR mapped length */
+#define PCI_MSIX_LEN 0x1000
+
+/** MSI-X vector offset */
+#define PCI_MSIX_VECTOR(n) ( (n) * 0x10 )
+
+/** MSI-X vector address low 32 bits */
+#define PCI_MSIX_ADDRESS_LO 0x0
+
+/** MSI-X vector address high 32 bits */
+#define PCI_MSIX_ADDRESS_HI 0x4
+
+/** MSI-X vector data */
+#define PCI_MSIX_DATA 0x8
+
+/** MSI-X vector control */
+#define PCI_MSIX_CONTROL 0xc
+#define PCI_MSIX_CONTROL_MASK 0x00000001	/**< Vector is masked */
+
+/** PCI MSI-X capability */
+struct pci_msix {
+	/** Capability offset */
+	unsigned int cap;
+	/** Number of vectors */
+	unsigned int count;
+	/** MSI-X table */
+	void *table;
+	/** Pending bit array */
+	void *pba;
+};
+
+extern int pci_msix_enable ( struct pci_device *pci, struct pci_msix *msix );
+extern void pci_msix_disable ( struct pci_device *pci, struct pci_msix *msix );
+extern void pci_msix_map ( struct pci_msix *msix, unsigned int vector,
+			   physaddr_t address, uint32_t data );
+extern void pci_msix_control ( struct pci_msix *msix, unsigned int vector,
+			       uint32_t mask );
+extern void pci_msix_dump ( struct pci_msix *msix, unsigned int vector );
+
+/**
+ * Mask MSI-X interrupt vector
+ *
+ * @v msix		MSI-X capability
+ * @v vector		MSI-X vector
+ */
+static inline __attribute__ (( always_inline )) void
+pci_msix_mask ( struct pci_msix *msix, unsigned int vector ) {
+
+	pci_msix_control ( msix, vector, PCI_MSIX_CONTROL_MASK );
+}
+
+/**
+ * Unmask MSI-X interrupt vector
+ *
+ * @v msix		MSI-X capability
+ * @v vector		MSI-X vector
+ */
+static inline __attribute__ (( always_inline )) void
+pci_msix_unmask ( struct pci_msix *msix, unsigned int vector ) {
+
+	pci_msix_control ( msix, vector, 0 );
+}
+
+#endif /* _IPXE_PCIMSIX_H */