mirror of
https://github.com/ipxe/ipxe
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Scott K Logan
committed by
Michael Brown
Michael Brown
parent
c28053027b
commit
aaf7a35207
403
src/drivers/net/ath/ath9k/ath9k_calib.c
Normal file
403
src/drivers/net/ath/ath9k/ath9k_calib.c
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@@ -0,0 +1,403 @@
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/*
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* Copyright (c) 2008-2011 Atheros Communications Inc.
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*
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* Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
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* Original from Linux kernel 3.0.1
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "hw.h"
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#include "hw-ops.h"
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/* Common calibration code */
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#define ATH9K_NF_TOO_HIGH -60
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static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
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{
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int16_t nfval;
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int16_t sort[ATH9K_NF_CAL_HIST_MAX];
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int i, j;
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for (i = 0; i < ATH9K_NF_CAL_HIST_MAX; i++)
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sort[i] = nfCalBuffer[i];
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for (i = 0; i < ATH9K_NF_CAL_HIST_MAX - 1; i++) {
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for (j = 1; j < ATH9K_NF_CAL_HIST_MAX - i; j++) {
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if (sort[j] > sort[j - 1]) {
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nfval = sort[j];
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sort[j] = sort[j - 1];
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sort[j - 1] = nfval;
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}
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}
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}
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nfval = sort[(ATH9K_NF_CAL_HIST_MAX - 1) >> 1];
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return nfval;
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}
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static struct ath_nf_limits *ath9k_hw_get_nf_limits(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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struct ath_nf_limits *limit;
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if (!chan || IS_CHAN_2GHZ(chan))
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limit = &ah->nf_2g;
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else
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limit = &ah->nf_5g;
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return limit;
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}
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static s16 ath9k_hw_get_default_nf(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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return ath9k_hw_get_nf_limits(ah, chan)->nominal;
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}
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static void ath9k_hw_update_nfcal_hist_buffer(struct ath_hw *ah,
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struct ath9k_hw_cal_data *cal,
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int16_t *nfarray)
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{
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struct ath_nf_limits *limit;
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struct ath9k_nfcal_hist *h;
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int high_nf_mid = 0;
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u8 chainmask = (ah->rxchainmask << 3) | ah->rxchainmask;
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int i;
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h = cal->nfCalHist;
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limit = ath9k_hw_get_nf_limits(ah, ah->curchan);
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for (i = 0; i < NUM_NF_READINGS; i++) {
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if (!(chainmask & (1 << i)) ||
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(i >= AR5416_MAX_CHAINS))
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continue;
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h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];
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if (++h[i].currIndex >= ATH9K_NF_CAL_HIST_MAX)
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h[i].currIndex = 0;
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if (h[i].invalidNFcount > 0) {
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h[i].invalidNFcount--;
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h[i].privNF = nfarray[i];
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} else {
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h[i].privNF =
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ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer);
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}
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if (!h[i].privNF)
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continue;
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if (h[i].privNF > limit->max) {
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high_nf_mid = 1;
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DBG2("ath9k: "
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"NFmid[%d] (%d) > MAX (%d), %s\n",
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i, h[i].privNF, limit->max,
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(cal->nfcal_interference ?
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"not corrected (due to interference)" :
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"correcting to MAX"));
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/*
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* Normally we limit the average noise floor by the
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* hardware specific maximum here. However if we have
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* encountered stuck beacons because of interference,
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* we bypass this limit here in order to better deal
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* with our environment.
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*/
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if (!cal->nfcal_interference)
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h[i].privNF = limit->max;
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}
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}
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/*
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* If the noise floor seems normal for all chains, assume that
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* there is no significant interference in the environment anymore.
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* Re-enable the enforcement of the NF maximum again.
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*/
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if (!high_nf_mid)
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cal->nfcal_interference = 0;
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}
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static int ath9k_hw_get_nf_thresh(struct ath_hw *ah,
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int band,
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int16_t *nft)
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{
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switch (band) {
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case NET80211_BAND_5GHZ:
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*nft = (int8_t)ah->eep_ops->get_eeprom(ah, EEP_NFTHRESH_5);
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break;
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case NET80211_BAND_2GHZ:
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*nft = (int8_t)ah->eep_ops->get_eeprom(ah, EEP_NFTHRESH_2);
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break;
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default:
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return 0;
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}
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return 1;
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}
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void ath9k_hw_reset_calibration(struct ath_hw *ah,
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struct ath9k_cal_list *currCal)
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{
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int i;
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ath9k_hw_setup_calibration(ah, currCal);
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currCal->calState = CAL_RUNNING;
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for (i = 0; i < AR5416_MAX_CHAINS; i++) {
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ah->meas0.sign[i] = 0;
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ah->meas1.sign[i] = 0;
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ah->meas2.sign[i] = 0;
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ah->meas3.sign[i] = 0;
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}
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ah->cal_samples = 0;
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}
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/* This is done for the currently configured channel */
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int ath9k_hw_reset_calvalid(struct ath_hw *ah)
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{
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struct ath9k_cal_list *currCal = ah->cal_list_curr;
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if (!ah->caldata)
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return 1;
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if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))
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return 1;
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if (currCal == NULL)
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return 1;
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if (currCal->calState != CAL_DONE) {
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DBG("ath9k: "
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"Calibration state incorrect, %d\n",
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currCal->calState);
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return 1;
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}
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if (!(ah->supp_cals & currCal->calData->calType))
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return 1;
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DBG("ath9k: "
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"Resetting Cal %d state for channel %d\n",
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currCal->calData->calType, (ah->dev->channels + ah->dev->channel)->center_freq);
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ah->caldata->CalValid &= ~currCal->calData->calType;
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currCal->calState = CAL_WAITING;
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return 0;
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}
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void ath9k_hw_start_nfcal(struct ath_hw *ah, int update)
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{
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if (ah->caldata)
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ah->caldata->nfcal_pending = 1;
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REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
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AR_PHY_AGC_CONTROL_ENABLE_NF);
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if (update)
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REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
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AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
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else
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REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
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AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
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REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
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}
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void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
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{
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struct ath9k_nfcal_hist *h = NULL;
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unsigned i, j;
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int32_t val;
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u8 chainmask = (ah->rxchainmask << 3) | ah->rxchainmask;
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s16 default_nf = ath9k_hw_get_default_nf(ah, chan);
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if (ah->caldata)
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h = ah->caldata->nfCalHist;
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for (i = 0; i < NUM_NF_READINGS; i++) {
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if (chainmask & (1 << i)) {
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s16 nfval;
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if (i >= AR5416_MAX_CHAINS)
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continue;
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if (h)
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nfval = h[i].privNF;
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else
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nfval = default_nf;
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val = REG_READ(ah, ah->nf_regs[i]);
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val &= 0xFFFFFE00;
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val |= (((u32) nfval << 1) & 0x1ff);
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REG_WRITE(ah, ah->nf_regs[i], val);
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}
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}
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/*
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* Load software filtered NF value into baseband internal minCCApwr
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* variable.
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*/
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REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
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AR_PHY_AGC_CONTROL_ENABLE_NF);
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REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
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AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
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REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
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/*
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* Wait for load to complete, should be fast, a few 10s of us.
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* The max delay was changed from an original 250us to 10000us
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* since 250us often results in NF load timeout and causes deaf
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* condition during stress testing 12/12/2009
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*/
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for (j = 0; j < 10000; j++) {
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if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
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AR_PHY_AGC_CONTROL_NF) == 0)
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break;
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udelay(10);
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}
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/*
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* We timed out waiting for the noisefloor to load, probably due to an
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* in-progress rx. Simply return here and allow the load plenty of time
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* to complete before the next calibration interval. We need to avoid
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* trying to load -50 (which happens below) while the previous load is
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* still in progress as this can cause rx deafness. Instead by returning
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* here, the baseband nf cal will just be capped by our present
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* noisefloor until the next calibration timer.
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*/
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if (j == 10000) {
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DBG("ath9k: "
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"Timeout while waiting for nf to load: AR_PHY_AGC_CONTROL=0x%x\n",
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REG_READ(ah, AR_PHY_AGC_CONTROL));
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return;
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}
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/*
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* Restore maxCCAPower register parameter again so that we're not capped
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* by the median we just loaded. This will be initial (and max) value
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* of next noise floor calibration the baseband does.
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*/
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ENABLE_REGWRITE_BUFFER(ah);
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for (i = 0; i < NUM_NF_READINGS; i++) {
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if (chainmask & (1 << i)) {
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if (i >= AR5416_MAX_CHAINS)
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continue;
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val = REG_READ(ah, ah->nf_regs[i]);
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val &= 0xFFFFFE00;
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val |= (((u32) (-50) << 1) & 0x1ff);
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REG_WRITE(ah, ah->nf_regs[i], val);
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}
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}
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REGWRITE_BUFFER_FLUSH(ah);
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}
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static void ath9k_hw_nf_sanitize(struct ath_hw *ah, s16 *nf)
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{
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struct ath_nf_limits *limit;
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int i;
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if (IS_CHAN_2GHZ(ah->curchan))
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limit = &ah->nf_2g;
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else
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limit = &ah->nf_5g;
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for (i = 0; i < NUM_NF_READINGS; i++) {
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if (!nf[i])
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continue;
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DBG2("ath9k: "
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"NF calibrated [%s] [chain %d] is %d\n",
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(i >= 3 ? "ext" : "ctl"), i % 3, nf[i]);
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if (nf[i] > ATH9K_NF_TOO_HIGH) {
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DBG("ath9k: "
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"NF[%d] (%d) > MAX (%d), correcting to MAX\n",
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i, nf[i], ATH9K_NF_TOO_HIGH);
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nf[i] = limit->max;
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} else if (nf[i] < limit->min) {
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DBG("ath9k: "
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"NF[%d] (%d) < MIN (%d), correcting to NOM\n",
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i, nf[i], limit->min);
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nf[i] = limit->nominal;
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}
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}
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}
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int ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan)
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{
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int16_t nf, nfThresh;
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int16_t nfarray[NUM_NF_READINGS] = { 0 };
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struct ath9k_nfcal_hist *h;
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struct net80211_channel *c = chan->chan;
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struct ath9k_hw_cal_data *caldata = ah->caldata;
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chan->channelFlags &= (~CHANNEL_CW_INT);
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if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
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DBG("ath9k: "
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"NF did not complete in calibration window\n");
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return 0;
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}
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ath9k_hw_do_getnf(ah, nfarray);
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ath9k_hw_nf_sanitize(ah, nfarray);
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nf = nfarray[0];
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if (ath9k_hw_get_nf_thresh(ah, c->band, &nfThresh)
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&& nf > nfThresh) {
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DBG2("ath9k: "
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"noise floor failed detected; detected %d, threshold %d\n",
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nf, nfThresh);
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chan->channelFlags |= CHANNEL_CW_INT;
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}
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if (!caldata) {
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chan->noisefloor = nf;
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return 0;
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}
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h = caldata->nfCalHist;
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caldata->nfcal_pending = 0;
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ath9k_hw_update_nfcal_hist_buffer(ah, caldata, nfarray);
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chan->noisefloor = h[0].privNF;
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return 1;
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}
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void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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struct ath9k_nfcal_hist *h;
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s16 default_nf;
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int i, j;
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ah->caldata->channel = chan->channel;
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ah->caldata->channelFlags = chan->channelFlags & ~CHANNEL_CW_INT;
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h = ah->caldata->nfCalHist;
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default_nf = ath9k_hw_get_default_nf(ah, chan);
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for (i = 0; i < NUM_NF_READINGS; i++) {
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h[i].currIndex = 0;
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h[i].privNF = default_nf;
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h[i].invalidNFcount = AR_PHY_CCA_FILTERWINDOW_LENGTH;
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for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) {
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h[i].nfCalBuffer[j] = default_nf;
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}
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}
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}
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Reference in New Issue
Block a user