mirror of
https://github.com/ipxe/ipxe
synced 2025-12-21 20:40:25 +03:00
[tg3] Fix driver for BCM5719, BCM5720, BCM5764M, BCM57762
Signed-off-by: Michael Brown <mcb30@ipxe.org>
This commit is contained in:
committed by
Michael Brown
parent
8f7cd88af5
commit
a05871d89a
@@ -247,11 +247,12 @@ static int tg3_open(struct net_device *dev)
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return err;
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return err;
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tpr->rx_std_iob_cnt = 0;
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tpr->rx_std_iob_cnt = 0;
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tg3_refill_prod_ring(tp);
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err = tg3_init_hw(tp, 1);
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err = tg3_init_hw(tp, 1);
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if (err != 0)
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if (err != 0)
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DBGC(tp->dev, "tg3_init_hw failed: %s\n", strerror(err));
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DBGC(tp->dev, "tg3_init_hw failed: %s\n", strerror(err));
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else
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tg3_refill_prod_ring(tp);
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return err;
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return err;
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}
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}
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@@ -301,7 +302,6 @@ static int tg3_transmit(struct net_device *dev, struct io_buffer *iob)
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struct tg3 *tp = netdev_priv(dev);
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struct tg3 *tp = netdev_priv(dev);
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u32 len, entry;
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u32 len, entry;
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dma_addr_t mapping;
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dma_addr_t mapping;
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u32 bmsr;
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if (tg3_tx_avail(tp) < 1) {
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if (tg3_tx_avail(tp) < 1) {
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DBGC(dev, "Transmit ring full\n");
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DBGC(dev, "Transmit ring full\n");
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@@ -323,14 +323,10 @@ static int tg3_transmit(struct net_device *dev, struct io_buffer *iob)
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/* Packets are ready, update Tx producer idx local and on card. */
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/* Packets are ready, update Tx producer idx local and on card. */
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tw32_tx_mbox(tp->prodmbox, entry);
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tw32_tx_mbox(tp->prodmbox, entry);
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writel(entry, tp->regs + MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
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tp->tx_prod = entry;
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tp->tx_prod = entry;
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mb();
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mb();
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tg3_readphy(tp, MII_BMSR, &bmsr);
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return 0;
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return 0;
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}
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}
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@@ -422,8 +418,10 @@ static void tg3_refill_prod_ring(struct tg3 *tp)
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tpr->rx_std_iob_cnt++;
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tpr->rx_std_iob_cnt++;
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}
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}
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tpr->rx_std_prod_idx = idx;
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if ((u32)idx != tpr->rx_std_prod_idx) {
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tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, idx);
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tpr->rx_std_prod_idx = idx;
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tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, idx);
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}
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}
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}
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static void tg3_rx_complete(struct net_device *dev)
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static void tg3_rx_complete(struct net_device *dev)
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@@ -469,7 +467,10 @@ static void tg3_rx_complete(struct net_device *dev)
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tpr->rx_std_iob_cnt--;
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tpr->rx_std_iob_cnt--;
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}
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}
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tp->rx_rcb_ptr = sw_idx;
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if (tp->rx_rcb_ptr != sw_idx) {
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tw32_rx_mbox(tp->consmbox, sw_idx);
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tp->rx_rcb_ptr = sw_idx;
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}
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tg3_refill_prod_ring(tp);
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tg3_refill_prod_ring(tp);
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}
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}
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@@ -480,7 +481,9 @@ static void tg3_poll(struct net_device *dev)
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struct tg3 *tp = netdev_priv(dev);
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struct tg3 *tp = netdev_priv(dev);
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/* ACK interrupts */
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/* ACK interrupts */
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tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00);
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/*
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*tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00);
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*/
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tp->hw_status->status &= ~SD_STATUS_UPDATED;
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tp->hw_status->status &= ~SD_STATUS_UPDATED;
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tg3_poll_link(tp);
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tg3_poll_link(tp);
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@@ -905,6 +908,7 @@ static struct pci_device_id tg3_nics[] = {
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PCI_ROM(0x14e4, 0x1684, "14e4-1684", "14e4-1684", 0),
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PCI_ROM(0x14e4, 0x1684, "14e4-1684", "14e4-1684", 0),
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PCI_ROM(0x14e4, 0x165b, "14e4-165b", "14e4-165b", 0),
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PCI_ROM(0x14e4, 0x165b, "14e4-165b", "14e4-165b", 0),
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PCI_ROM(0x14e4, 0x1681, "14e4-1681", "14e4-1681", 0),
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PCI_ROM(0x14e4, 0x1681, "14e4-1681", "14e4-1681", 0),
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PCI_ROM(0x14e4, 0x1682, "14e4-1682", "14e4-1682", 0),
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PCI_ROM(0x14e4, 0x1680, "14e4-1680", "14e4-1680", 0),
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PCI_ROM(0x14e4, 0x1680, "14e4-1680", "14e4-1680", 0),
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PCI_ROM(0x14e4, 0x1688, "14e4-1688", "14e4-1688", 0),
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PCI_ROM(0x14e4, 0x1688, "14e4-1688", "14e4-1688", 0),
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PCI_ROM(0x14e4, 0x1689, "14e4-1689", "14e4-1689", 0),
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PCI_ROM(0x14e4, 0x1689, "14e4-1689", "14e4-1689", 0),
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@@ -153,6 +153,7 @@
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#define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
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#define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
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#define TG3_BDINFO_SIZE 0x10UL
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#define TG3_BDINFO_SIZE 0x10UL
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#define RX_STD_MAX_SIZE 1536
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#define TG3_RX_STD_MAX_SIZE_5700 512
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#define TG3_RX_STD_MAX_SIZE_5700 512
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#define TG3_RX_STD_MAX_SIZE_5717 2048
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#define TG3_RX_STD_MAX_SIZE_5717 2048
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#define TG3_RX_JMB_MAX_SIZE_5700 256
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#define TG3_RX_JMB_MAX_SIZE_5700 256
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@@ -182,6 +183,7 @@
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#define TG3PCI_DEVICE_TIGON3_57781 0x16b1
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#define TG3PCI_DEVICE_TIGON3_57781 0x16b1
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#define TG3PCI_DEVICE_TIGON3_57785 0x16b5
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#define TG3PCI_DEVICE_TIGON3_57785 0x16b5
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#define TG3PCI_DEVICE_TIGON3_57761 0x16b0
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#define TG3PCI_DEVICE_TIGON3_57761 0x16b0
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#define TG3PCI_DEVICE_TIGON3_57762 0x1682
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#define TG3PCI_DEVICE_TIGON3_57765 0x16b4
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#define TG3PCI_DEVICE_TIGON3_57765 0x16b4
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#define TG3PCI_DEVICE_TIGON3_57791 0x16b2
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#define TG3PCI_DEVICE_TIGON3_57791 0x16b2
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#define TG3PCI_DEVICE_TIGON3_57795 0x16b6
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#define TG3PCI_DEVICE_TIGON3_57795 0x16b6
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@@ -434,6 +434,7 @@ int tg3_get_invariants(struct tg3 *tp)
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else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
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else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
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tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
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tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
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tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
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tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
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tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
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tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
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tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
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tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
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tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
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tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
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tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
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@@ -2127,9 +2128,12 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
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val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
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if (tg3_flag(tp, 57765_PLUS))
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val |= (RX_STD_MAX_SIZE << 2);
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tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
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tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
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tpr->rx_std_prod_idx = TG3_DEF_RX_RING_PENDING;
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tpr->rx_std_prod_idx = 0;
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/* std prod index is updated by tg3_refill_prod_ring() */
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/* std prod index is updated by tg3_refill_prod_ring() */
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tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, 0);
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tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, 0);
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@@ -2137,6 +2141,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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tg3_rings_reset(tp);
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tg3_rings_reset(tp);
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__tg3_set_mac_addr(tp,0);
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#define TG3_MAX_MTU 1522
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#define TG3_MAX_MTU 1522
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/* MTU + ethernet header + FCS + optional VLAN tag */
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/* MTU + ethernet header + FCS + optional VLAN tag */
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tw32(MAC_RX_MTU_SIZE, TG3_MAX_MTU);
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tw32(MAC_RX_MTU_SIZE, TG3_MAX_MTU);
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@@ -1008,12 +1008,11 @@ skip_phy_reset:
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void tg3_poll_link(struct tg3 *tp)
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void tg3_poll_link(struct tg3 *tp)
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{ DBGP("%s\n", __func__);
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{ DBGP("%s\n", __func__);
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u32 mac_stat;
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if (tp->hw_status->status & SD_STATUS_LINK_CHG) {
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DBGC(tp->dev,"link_changed\n");
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mac_stat = tr32(MAC_STATUS);
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tp->hw_status->status &= ~SD_STATUS_LINK_CHG;
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if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
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tg3_setup_phy(tp, 0);
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tg3_setup_phy(tp, 0);
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}
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}
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}
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static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
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static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
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@@ -1506,9 +1505,8 @@ relink:
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tw32_f(MAC_MODE, tp->mac_mode);
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tw32_f(MAC_MODE, tp->mac_mode);
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udelay(40);
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udelay(40);
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/* We always use the link change register */
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/* Enabled attention when the link has changed state. */
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/* NOTE: this freezes for mdc? */
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tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
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tw32_f(MAC_EVENT, 0);
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udelay(40);
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udelay(40);
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
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