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https://github.com/ipxe/ipxe
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[librm] Support ioremap() for addresses above 4GB in a 64-bit build
Signed-off-by: Michael Brown <mcb30@ipxe.org>
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@@ -9,4 +9,6 @@
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#include <ipxe/iomap_pages.h>
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#endif /* _BITS_IOMAP_H */
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24
src/arch/x86/include/ipxe/iomap_pages.h
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24
src/arch/x86/include/ipxe/iomap_pages.h
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@@ -0,0 +1,24 @@
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#ifndef _IPXE_IOMAP_PAGES_H
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#define _IPXE_IOMAP_PAGES_H
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/** @file
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*
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* I/O mapping API using page tables
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*
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*/
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#ifdef IOMAP_PAGES
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#define IOMAP_PREFIX_pages
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#else
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#define IOMAP_PREFIX_pages __pages_
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#endif
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static inline __always_inline unsigned long
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IOMAP_INLINE ( pages, io_to_bus ) ( volatile const void *io_addr ) {
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/* Not easy to do; just return the CPU address for debugging purposes */
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return ( ( intptr_t ) io_addr );
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}
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#endif /* _IPXE_IOMAP_PAGES_H */
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@@ -378,6 +378,51 @@ struct interrupt_vector {
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extern void set_interrupt_vector ( unsigned int intr, void *vector );
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/** A page table */
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struct page_table {
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/** Page address and flags */
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uint64_t page[512];
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};
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/** Page flags */
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enum page_flags {
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/** Page is present */
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PAGE_P = 0x01,
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/** Page is writable */
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PAGE_RW = 0x02,
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/** Page is accessible by user code */
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PAGE_US = 0x04,
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/** Page-level write-through */
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PAGE_PWT = 0x08,
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/** Page-level cache disable */
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PAGE_PCD = 0x10,
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/** Page is a large page */
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PAGE_PS = 0x80,
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/** Page is the last page in an allocation
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*
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* This bit is ignored by the hardware. We use it to track
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* the size of allocations made by ioremap().
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*/
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PAGE_LAST = 0x800,
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};
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/** The I/O space page table */
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extern struct page_table io_pages;
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/** I/O page size
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*
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* We choose to use 2MB pages for I/O space, to minimise the number of
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* page table entries required.
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*/
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#define IO_PAGE_SIZE 0x200000UL
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/** I/O page base address
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*
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* We choose to place I/O space immediately above the identity-mapped
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* 32-bit address space.
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*/
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#define IO_BASE ( ( void * ) 0x100000000ULL )
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#endif /* ASSEMBLY */
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#endif /* LIBRM_H */
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