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https://github.com/ipxe/ipxe
synced 2026-01-22 03:32:59 +03:00
[riscv] Hold virtual address offset in the thread pointer register
iPXE does not make use of any thread-local storage. Use the otherwise
unused thread pointer register ("tp") to hold the current value of
the virtual address offset, rather than using a global variable.
This ensures that virt_offset can be made valid even during very early
initialisation (when iPXE may be executing directly from read-only
memory and so cannot update a global variable).
Signed-off-by: Michael Brown <mcb30@ipxe.org>
This commit is contained in:
Michael Brown
33
src/arch/riscv/include/bits/virt_offset.h
Normal file
33
src/arch/riscv/include/bits/virt_offset.h
Normal file
@@ -0,0 +1,33 @@
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#ifndef _BITS_VIRT_OFFSET_H
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#define _BITS_VIRT_OFFSET_H
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/** @file
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*
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* RISCV-specific virtual address offset
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*
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* We use the thread pointer register (tp) to hold the virtual address
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* offset, so that virtual-to-physical address translations work as
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* expected even while we are executing directly from read-only memory
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* (and so cannot store a value in a global virt_offset variable).
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*
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*/
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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/**
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* Read virtual address offset held in thread pointer register
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*
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* @ret virt_offset Virtual address offset
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*/
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static inline __attribute__ (( const, always_inline )) unsigned long
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tp_virt_offset ( void ) {
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register unsigned long tp asm ( "tp" );
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__asm__ ( "" : "=r" ( tp ) );
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return tp;
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}
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/** Always read thread pointer register to get virtual address offset */
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#define virt_offset tp_virt_offset()
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#endif /* _BITS_VIRT_OFFSET_H */
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@@ -41,13 +41,6 @@ prefix_virt:
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.dword _prefix
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.size prefix_virt, . - prefix_virt
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/* Current virtual address offset */
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.section ".data.virt_offset", "aw", @progbits
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.globl virt_offset
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virt_offset:
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.space ( __riscv_xlen / 8 )
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.size virt_offset, . - virt_offset
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/*****************************************************************************
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*
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* Print message to debug console
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@@ -311,7 +304,7 @@ apply_relocs_done:
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*
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* Returns:
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*
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* a0 - Virtual address offset
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* tp - Virtual address offset
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* pc - Updated to a virtual address if paging enabled
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*
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*/
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@@ -418,10 +411,11 @@ paging_mode_names:
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*
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* Parameters:
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*
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* a0 - Virtual address offset
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* tp - Virtual address offset
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*
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* Returns:
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*
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* tp - Virtual address offset (zeroed)
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* pc - Updated to a physical address
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*
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*/
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@@ -449,7 +443,7 @@ paging_mode_names:
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*
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* Returns:
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*
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* a0 - Virtual address offset
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* tp - Virtual address offset
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* pc - Updated to a virtual address if paging enabled
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*
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* A 4kB 64-bit page table contains 512 8-byte PTEs. We choose to use
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@@ -510,21 +504,20 @@ paging_mode_names:
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enable_paging_64:
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/* Register usage:
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*
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* a0 - return value (virtual address offset)
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* tp - return value (virtual address offset)
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* a0 - page table base address
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* a1 - currently attempted paging level
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* a2 - enabled paging level
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* a3 - page table base address
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* a4 - PTE pointer
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* a5 - PTE stride
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* a3 - PTE pointer
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* a4 - PTE stride
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*/
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progress " paging:"
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mv a3, a0
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li a1, SATP_MODE_SV57
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/* Calculate virtual address offset */
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LOADN t0, prefix_virt
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la t1, _prefix
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sub a0, t1, t0
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sub tp, t1, t0
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enable_paging_64_loop:
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@@ -534,50 +527,50 @@ enable_paging_64_loop:
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* a1 == 9 == Sv48: PPN[3] LSB is PTE bit 37 => stride := 1 << 37
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* a1 == 8 == Sv39: PPN[2] LSB is PTE bit 28 => stride := 1 << 28
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*
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* and so we calculate stride a5 := ( 1 << ( 9 * a1 - 44 ) )
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* and so we calculate stride a4 := ( 1 << ( 9 * a1 - 44 ) )
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*/
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slli a5, a1, 3
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add a5, a5, a1
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addi a5, a5, -44
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slli a4, a1, 3
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add a4, a4, a1
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addi a4, a4, -44
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li t0, 1
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sll a5, t0, a5
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sll a4, t0, a4
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/* Construct PTE[0-255] for identity map */
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mv a4, a3
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mv a3, a0
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li t0, ( PTE_COUNT / 2 )
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li t1, PTE_LEAF
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1: STOREN t1, (a4)
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addi a4, a4, PTE_SIZE
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add t1, t1, a5
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1: STOREN t1, (a3)
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addi a3, a3, PTE_SIZE
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add t1, t1, a4
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addi t0, t0, -1
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bgtz t0, 1b
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/* Zero PTE[256-511] */
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li t0, ( PTE_COUNT / 2 )
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1: STOREN zero, (a4)
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addi a4, a4, PTE_SIZE
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1: STOREN zero, (a3)
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addi a3, a3, PTE_SIZE
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addi t0, t0, -1
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bgtz t0, 1b
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/* Construct PTE[511] as next level page table pointer */
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srli t0, a3, PTE_PPN_SHIFT
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srli t0, a0, PTE_PPN_SHIFT
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ori t0, t0, PTE_V
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STOREN t0, -PTE_SIZE(a4)
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STOREN t0, -PTE_SIZE(a3)
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/* Calculate PTE[x] address for iPXE virtual address map */
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LOADN t0, prefix_virt
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srli t0, t0, VPN1_LSB
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andi t0, t0, ( PTE_COUNT - 1 )
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slli t0, t0, PTE_SIZE_LOG2
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add a4, a3, t0
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add a3, a0, t0
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/* Calculate PTE stride for iPXE virtual address map
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*
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* PPN[1] LSB is PTE bit 19 in all paging modes, and so the
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* stride is always ( 1 << 19 )
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*/
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li a5, 1
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slli a5, a5, PTE_PPN1_LSB
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li a4, 1
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slli a4, a4, PTE_PPN1_LSB
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/* Construct PTE[x-y] for iPXE virtual address map */
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la t0, _prefix
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@@ -585,14 +578,14 @@ enable_paging_64_loop:
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ori t0, t0, PTE_LEAF
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la t1, _ebss
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srli t1, t1, PTE_PPN_SHIFT
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1: STOREN t0, (a4)
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addi a4, a4, PTE_SIZE
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add t0, t0, a5
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1: STOREN t0, (a3)
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addi a3, a3, PTE_SIZE
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add t0, t0, a4
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ble t0, t1, 1b
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/* Attempt to enable paging, and read back active paging level */
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slli t0, a1, SATP_MODE_SHIFT
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srli t1, a3, PAGE_SHIFT
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srli t1, a0, PAGE_SHIFT
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or t0, t0, t1
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csrrw zero, satp, t0
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sfence.vma
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@@ -604,10 +597,10 @@ enable_paging_64_loop:
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addi a1, a1, -1
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li t0, SATP_MODE_SV39
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bge a1, t0, enable_paging_64_loop
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mv a0, zero
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mv tp, zero
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1:
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/* Adjust return address to a virtual address */
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sub ra, ra, a0
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sub ra, ra, tp
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/* Return, with or without paging enabled */
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paging_mode_name a2
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@@ -625,10 +618,11 @@ enable_paging_64_loop:
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*
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* Parameters:
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*
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* a0 - Virtual address offset
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* tp - Virtual address offset
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*
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* Returns:
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*
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* tp - Virtual address offset (zeroed)
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* pc - Updated to a physical address
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*
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*/
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@@ -637,13 +631,13 @@ enable_paging_64_loop:
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disable_paging_64:
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/* Register usage:
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*
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* a0 - virtual address offset
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* tp - virtual address offset
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*/
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/* Jump to physical address */
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la t0, 1f
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bgez t0, 1f
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add t0, t0, a0
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add t0, t0, tp
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jr t0
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1:
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/* Disable paging */
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@@ -652,9 +646,10 @@ disable_paging_64:
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/* Update return address to a physical address */
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bgez ra, 1f
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add ra, ra, a0
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add ra, ra, tp
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1:
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/* Return with paging disabled */
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/* Return with paging disabled and virtual offset zeroed */
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mv tp, zero
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ret
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.size disable_paging_64, . - disable_paging_64
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@@ -677,7 +672,7 @@ disable_paging_64:
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*
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* Returns:
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*
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* a0 - Virtual address offset
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* tp - Virtual address offset
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* pc - Updated to a virtual address if paging enabled
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*
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* A 4kB 32-bit page table contains 1024 4-byte PTEs. We choose to
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@@ -698,29 +693,28 @@ disable_paging_64:
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enable_paging_32:
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/* Register usage:
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*
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* a0 - return value (virtual address offset)
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* tp - return value (virtual address offset)
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* a0 - page table base address
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* a1 - enabled paging level
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* a2 - page table base address
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* a3 - PTE pointer
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* a4 - saved content of temporarily modified PTE
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* a2 - PTE pointer
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* a3 - saved content of temporarily modified PTE
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*/
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progress " paging:"
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mv a2, a0
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/* Calculate virtual address offset */
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LOADN t0, prefix_virt
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la t1, _prefix
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sub a0, t1, t0
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sub tp, t1, t0
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/* Construct PTEs for circular map */
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mv a3, a2
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mv a2, a0
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li t0, PTE_COUNT
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mv t1, a0
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mv t1, tp
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ori t1, t1, ( PTE_LEAF << PTE_PPN_SHIFT )
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li t2, ( 1 << ( PTE_PPN1_LSB + PTE_PPN_SHIFT ) )
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1: srli t3, t1, PTE_PPN_SHIFT
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STOREN t3, (a3)
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addi a3, a3, PTE_SIZE
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STOREN t3, (a2)
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addi a2, a2, PTE_SIZE
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add t1, t1, t2
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addi t0, t0, -1
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bgtz t0, 1b
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@@ -729,20 +723,20 @@ enable_paging_32:
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la t0, enable_paging_32_xstart
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srli t0, t0, VPN1_LSB
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slli t1, t0, PTE_SIZE_LOG2
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add a3, a2, t1
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LOADN a4, (a3)
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add a2, a0, t1
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LOADN a3, (a2)
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slli t0, t0, PTE_PPN1_LSB
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ori t0, t0, PTE_LEAF
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STOREN t0, (a3)
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STOREN t0, (a2)
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/* Adjust PTE pointer to a virtual address */
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sub a3, a3, a0
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sub a2, a2, tp
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/* Attempt to enable paging, and read back active paging level */
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la t0, 1f
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sub t0, t0, a0
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sub t0, t0, tp
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li t1, ( SATP_MODE_SV32 << SATP_MODE_SHIFT )
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srli t2, a2, PAGE_SHIFT
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srli t2, a0, PAGE_SHIFT
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or t1, t1, t2
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.balign enable_paging_32_xalign
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/* Start of transition code */
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@@ -753,7 +747,7 @@ enable_paging_32_xstart:
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beqz a1, 2f
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jr t0
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1: /* Restore temporarily modified PTE */
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STOREN a4, (a3)
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STOREN a3, (a2)
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sfence.vma
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/* End of transition code */
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.equ enable_paging_32_xlen, . - enable_paging_32_xstart
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@@ -761,10 +755,10 @@ enable_paging_32_xstart:
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/* Clear virtual address offset if paging is not enabled */
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bnez a1, 1f
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mv a0, zero
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mv tp, zero
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1:
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/* Adjust return address to a virtual address */
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sub ra, ra, a0
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sub ra, ra, tp
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/* Return, with or without paging enabled */
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paging_mode_name a1
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@@ -786,10 +780,11 @@ enable_paging_32_xstart:
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*
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* Parameters:
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*
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* a0 - Virtual address offset
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* tp - Virtual address offset
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*
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* Returns:
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*
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* tp - Virtual address offset (zeroed)
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* pc - Updated to a physical address
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*
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*/
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@@ -800,34 +795,34 @@ enable_paging_32_xstart:
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disable_paging_32:
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/* Register usage:
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*
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* a0 - virtual address offset
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* a1 - page table address
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* a2 - transition PTE pointer
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* a3 - transition PTE content
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* tp - virtual address offset
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* a0 - page table address
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* a1 - transition PTE pointer
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* a2 - transition PTE content
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*/
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/* Get page table address, and exit if paging is already disabled */
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csrr a1, satp
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beqz a1, 99f
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slli a1, a1, PAGE_SHIFT
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sub a1, a1, a0
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csrr a0, satp
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beqz a0, 99f
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slli a0, a0, PAGE_SHIFT
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sub a0, a0, tp
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/* Prepare for modifying transition PTE */
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la t0, disable_paging_32_xstart
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add t0, t0, a0
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add t0, t0, tp
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srli t0, t0, VPN1_LSB
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slli a2, t0, PTE_SIZE_LOG2
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add a2, a2, a1
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slli a3, t0, PTE_PPN1_LSB
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ori a3, a3, PTE_LEAF
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slli a1, t0, PTE_SIZE_LOG2
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add a1, a1, a0
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slli a2, t0, PTE_PPN1_LSB
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ori a2, a2, PTE_LEAF
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/* Jump to physical address in transition PTE, and disable paging */
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la t0, 1f
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add t0, t0, a0
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add t0, t0, tp
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.balign disable_paging_32_xalign
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/* Start of transition code */
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disable_paging_32_xstart:
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STOREN a3, (a2)
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STOREN a2, (a1)
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sfence.vma
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jr t0
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1: csrw satp, zero
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@@ -836,9 +831,10 @@ disable_paging_32_xstart:
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.equ disable_paging_32_xlen, . - disable_paging_32_xstart
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/* Update return address to a physical address */
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add ra, ra, a0
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add ra, ra, tp
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99: /* Return with paging disabled */
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99: /* Return with paging disabled and virtual offset zeroed */
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mv tp, zero
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ret
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.size disable_paging_32, . - disable_paging_32
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@@ -57,6 +57,9 @@ progress_\@:
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.org 0
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.globl _sbi_start
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_sbi_start:
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/* Initialise virtual address offset */
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mv tp, zero
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/* Preserve arguments */
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mv s0, a0
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mv s1, a1
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