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https://github.com/ipxe/ipxe
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[serial] Add general abstraction of a 16550-compatible UART
Signed-off-by: Michael Brown <mcb30@ipxe.org>
This commit is contained in:
@@ -89,6 +89,7 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#define ERRFILE_i2c_bit ( ERRFILE_DRIVER | 0x00120000 )
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#define ERRFILE_spi_bit ( ERRFILE_DRIVER | 0x00130000 )
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#define ERRFILE_nvsvpd ( ERRFILE_DRIVER | 0x00140000 )
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#define ERRFILE_uart ( ERRFILE_DRIVER | 0x00150000 )
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#define ERRFILE_3c509 ( ERRFILE_DRIVER | 0x00200000 )
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#define ERRFILE_bnx2 ( ERRFILE_DRIVER | 0x00210000 )
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131
src/include/ipxe/uart.h
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131
src/include/ipxe/uart.h
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@@ -0,0 +1,131 @@
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#ifndef _IPXE_UART_H
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#define _IPXE_UART_H
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/** @file
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*
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* 16550-compatible UART
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*
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*/
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#include <stdint.h>
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/** Transmitter holding register */
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#define UART_THR 0x00
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/** Receiver buffer register */
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#define UART_RBR 0x00
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/** Interrupt enable register */
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#define UART_IER 0x01
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/** FIFO control register */
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#define UART_FCR 0x02
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#define UART_FCR_FE 0x01 /**< FIFO enable */
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/** Line control register */
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#define UART_LCR 0x03
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#define UART_LCR_WLS0 0x01 /**< Word length select bit 0 */
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#define UART_LCR_WLS1 0x02 /**< Word length select bit 1 */
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#define UART_LCR_STB 0x04 /**< Number of stop bits */
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#define UART_LCR_PEN 0x08 /**< Parity enable */
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#define UART_LCR_EPS 0x10 /**< Even parity select */
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#define UART_LCR_DLAB 0x80 /**< Divisor latch access bit */
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#define UART_LCR_WORD_LEN(x) ( ( (x) - 5 ) << 0 ) /**< Word length */
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#define UART_LCR_STOP_BITS(x) ( ( (x) - 1 ) << 2 ) /**< Stop bits */
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#define UART_LCR_PARITY(x) ( ( (x) - 0 ) << 3 ) /**< Parity */
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/**
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* Calculate line control register value
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*
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* @v word_len Word length (5-8)
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* @v parity Parity (0=none, 1=odd, 3=even)
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* @v stop_bits Stop bits (1-2)
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* @ret lcr Line control register value
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*/
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#define UART_LCR_WPS( word_len, parity, stop_bits ) \
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( UART_LCR_WORD_LEN ( (word_len) ) | \
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UART_LCR_PARITY ( (parity) ) | \
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UART_LCR_STOP_BITS ( (stop_bits) ) )
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/** Default LCR value: 8 data bits, no parity, one stop bit */
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#define UART_LCR_8N1 UART_LCR_WPS ( 8, 0, 1 )
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/** Modem control register */
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#define UART_MCR 0x04
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#define UART_MCR_DTR 0x01 /**< Data terminal ready */
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#define UART_MCR_RTS 0x02 /**< Request to send */
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/** Line status register */
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#define UART_LSR 0x05
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#define UART_LSR_DR 0x01 /**< Data ready */
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#define UART_LSR_THRE 0x20 /**< Transmitter holding register empty */
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#define UART_LSR_TEMT 0x40 /**< Transmitter empty */
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/** Scratch register */
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#define UART_SCR 0x07
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/** Divisor latch (least significant byte) */
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#define UART_DLL 0x00
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/** Divisor latch (most significant byte) */
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#define UART_DLM 0x01
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/** Maximum baud rate */
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#define UART_MAX_BAUD 115200
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/** A 16550-compatible UART */
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struct uart {
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/** I/O port base address */
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void *base;
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/** Baud rate divisor */
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uint16_t divisor;
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/** Line control register */
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uint8_t lcr;
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};
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/** Symbolic names for port indexes */
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enum uart_port {
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COM1 = 1,
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COM2 = 2,
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COM3 = 3,
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COM4 = 4,
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};
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#include <bits/uart.h>
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void uart_write ( struct uart *uart, unsigned int addr, uint8_t data );
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uint8_t uart_read ( struct uart *uart, unsigned int addr );
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int uart_select ( struct uart *uart, unsigned int port );
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/**
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* Check if received data is ready
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*
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* @v uart UART
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* @ret ready Data is ready
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*/
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static inline int uart_data_ready ( struct uart *uart ) {
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uint8_t lsr;
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lsr = uart_read ( uart, UART_LSR );
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return ( lsr & UART_LSR_DR );
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}
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/**
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* Receive data
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*
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* @v uart UART
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* @ret data Data
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*/
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static inline uint8_t uart_receive ( struct uart *uart ) {
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return uart_read ( uart, UART_RBR );
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}
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extern void uart_transmit ( struct uart *uart, uint8_t data );
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extern void uart_flush ( struct uart *uart );
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extern int uart_init ( struct uart *uart, unsigned int baud, uint8_t lcr );
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#endif /* _IPXE_UART_H */
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