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https://github.com/ipxe/ipxe
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[ioapi] Generalise i386 raw I/O API to x86
Signed-off-by: Michael Brown <mcb30@ipxe.org>
This commit is contained in:
Michael Brown
101
src/arch/x86/core/x86_io.c
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101
src/arch/x86/core/x86_io.c
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/*
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* Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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FILE_LICENCE ( GPL2_OR_LATER );
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#include <ipxe/io.h>
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#include <ipxe/x86_io.h>
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/** @file
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*
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* iPXE I/O API for x86
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*
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*/
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/**
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* Read 64-bit qword from memory-mapped device
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*
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* @v io_addr I/O address
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* @ret data Value read
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*
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* This routine uses MMX instructions.
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*/
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static __unused uint64_t i386_readq ( volatile uint64_t *io_addr ) {
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uint64_t data;
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__asm__ __volatile__ ( "pushl %%edx\n\t"
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"pushl %%eax\n\t"
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"movq (%1), %%mm0\n\t"
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"movq %%mm0, (%%esp)\n\t"
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"popl %%eax\n\t"
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"popl %%edx\n\t"
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"emms\n\t"
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: "=A" ( data ) : "r" ( io_addr ) );
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return data;
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}
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/**
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* Write 64-bit qword to memory-mapped device
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*
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* @v data Value to write
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* @v io_addr I/O address
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*
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* This routine uses MMX instructions.
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*/
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static __unused void i386_writeq ( uint64_t data, volatile uint64_t *io_addr ) {
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__asm__ __volatile__ ( "pushl %%edx\n\t"
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"pushl %%eax\n\t"
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"movq (%%esp), %%mm0\n\t"
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"movq %%mm0, (%1)\n\t"
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"popl %%eax\n\t"
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"popl %%edx\n\t"
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"emms\n\t"
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: : "A" ( data ), "r" ( io_addr ) );
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}
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PROVIDE_IOAPI_INLINE ( x86, phys_to_bus );
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PROVIDE_IOAPI_INLINE ( x86, bus_to_phys );
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PROVIDE_IOAPI_INLINE ( x86, ioremap );
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PROVIDE_IOAPI_INLINE ( x86, iounmap );
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PROVIDE_IOAPI_INLINE ( x86, io_to_bus );
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PROVIDE_IOAPI_INLINE ( x86, readb );
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PROVIDE_IOAPI_INLINE ( x86, readw );
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PROVIDE_IOAPI_INLINE ( x86, readl );
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PROVIDE_IOAPI_INLINE ( x86, writeb );
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PROVIDE_IOAPI_INLINE ( x86, writew );
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PROVIDE_IOAPI_INLINE ( x86, writel );
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PROVIDE_IOAPI_INLINE ( x86, inb );
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PROVIDE_IOAPI_INLINE ( x86, inw );
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PROVIDE_IOAPI_INLINE ( x86, inl );
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PROVIDE_IOAPI_INLINE ( x86, outb );
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PROVIDE_IOAPI_INLINE ( x86, outw );
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PROVIDE_IOAPI_INLINE ( x86, outl );
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PROVIDE_IOAPI_INLINE ( x86, insb );
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PROVIDE_IOAPI_INLINE ( x86, insw );
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PROVIDE_IOAPI_INLINE ( x86, insl );
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PROVIDE_IOAPI_INLINE ( x86, outsb );
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PROVIDE_IOAPI_INLINE ( x86, outsw );
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PROVIDE_IOAPI_INLINE ( x86, outsl );
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PROVIDE_IOAPI_INLINE ( x86, iodelay );
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PROVIDE_IOAPI_INLINE ( x86, mb );
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#ifdef __x86_64__
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PROVIDE_IOAPI_INLINE ( x86, readq );
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PROVIDE_IOAPI_INLINE ( x86, writeq );
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#else
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PROVIDE_IOAPI ( x86, readq, i386_readq );
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PROVIDE_IOAPI ( x86, writeq, i386_writeq );
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#endif
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14
src/arch/x86/include/bits/io.h
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14
src/arch/x86/include/bits/io.h
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#ifndef _BITS_IO_H
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#define _BITS_IO_H
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/** @file
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*
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* x86-specific I/O API implementations
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*
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*/
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FILE_LICENCE ( GPL2_OR_LATER );
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#include <ipxe/x86_io.h>
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#endif /* _BITS_IO_H */
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159
src/arch/x86/include/ipxe/x86_io.h
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159
src/arch/x86/include/ipxe/x86_io.h
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#ifndef _IPXE_X86_IO_H
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#define _IPXE_X86_IO_H
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/** @file
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*
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* iPXE I/O API for x86
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*
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* x86 uses direct pointer dereferences for accesses to memory-mapped
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* I/O space, and the inX/outX instructions for accesses to
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* port-mapped I/O space.
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*
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* 64-bit atomic accesses (readq() and writeq()) use MMX instructions
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* under i386, and will crash original Pentium and earlier CPUs.
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* Fortunately, no hardware that requires atomic 64-bit accesses will
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* physically fit into a machine with such an old CPU anyway.
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*/
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FILE_LICENCE ( GPL2_OR_LATER );
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#ifdef IOAPI_X86
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#define IOAPI_PREFIX_x86
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#else
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#define IOAPI_PREFIX_x86 __x86_
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#endif
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/*
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* Memory space mappings
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*
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*/
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/*
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* Physical<->Bus and Bus<->I/O address mappings
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*
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*/
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static inline __always_inline unsigned long
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IOAPI_INLINE ( x86, phys_to_bus ) ( unsigned long phys_addr ) {
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return phys_addr;
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}
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static inline __always_inline unsigned long
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IOAPI_INLINE ( x86, bus_to_phys ) ( unsigned long bus_addr ) {
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return bus_addr;
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}
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static inline __always_inline void *
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IOAPI_INLINE ( x86, ioremap ) ( unsigned long bus_addr, size_t len __unused ) {
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return phys_to_virt ( bus_addr );
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}
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static inline __always_inline void
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IOAPI_INLINE ( x86, iounmap ) ( volatile const void *io_addr __unused ) {
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/* Nothing to do */
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}
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static inline __always_inline unsigned long
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IOAPI_INLINE ( x86, io_to_bus ) ( volatile const void *io_addr ) {
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return virt_to_phys ( io_addr );
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}
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/*
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* MMIO reads and writes up to native word size
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*
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*/
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#define X86_READX( _api_func, _type ) \
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static inline __always_inline _type \
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IOAPI_INLINE ( x86, _api_func ) ( volatile _type *io_addr ) { \
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return *io_addr; \
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}
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X86_READX ( readb, uint8_t );
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X86_READX ( readw, uint16_t );
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X86_READX ( readl, uint32_t );
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#ifdef __x86_64__
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X86_READX ( readq, uint64_t );
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#endif
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#define X86_WRITEX( _api_func, _type ) \
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static inline __always_inline void \
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IOAPI_INLINE ( x86, _api_func ) ( _type data, \
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volatile _type *io_addr ) { \
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*io_addr = data; \
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}
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X86_WRITEX ( writeb, uint8_t );
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X86_WRITEX ( writew, uint16_t );
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X86_WRITEX ( writel, uint32_t );
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#ifdef __x86_64__
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X86_WRITEX ( writeq, uint64_t );
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#endif
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/*
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* PIO reads and writes up to 32 bits
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*
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*/
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#define X86_INX( _insn_suffix, _type, _reg_prefix ) \
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static inline __always_inline _type \
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IOAPI_INLINE ( x86, in ## _insn_suffix ) ( volatile _type *io_addr ) { \
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_type data; \
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__asm__ __volatile__ ( "in" #_insn_suffix " %w1, %" _reg_prefix "0" \
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: "=a" ( data ) : "Nd" ( io_addr ) ); \
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return data; \
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} \
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static inline __always_inline void \
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IOAPI_INLINE ( x86, ins ## _insn_suffix ) ( volatile _type *io_addr, \
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_type *data, \
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unsigned int count ) { \
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unsigned int discard_D; \
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__asm__ __volatile__ ( "rep ins" #_insn_suffix \
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: "=D" ( discard_D ) \
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: "d" ( io_addr ), "c" ( count ), \
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"0" ( data ) ); \
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}
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X86_INX ( b, uint8_t, "b" );
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X86_INX ( w, uint16_t, "w" );
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X86_INX ( l, uint32_t, "k" );
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#define X86_OUTX( _insn_suffix, _type, _reg_prefix ) \
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static inline __always_inline void \
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IOAPI_INLINE ( x86, out ## _insn_suffix ) ( _type data, \
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volatile _type *io_addr ) { \
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__asm__ __volatile__ ( "out" #_insn_suffix " %" _reg_prefix "0, %w1" \
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: : "a" ( data ), "Nd" ( io_addr ) ); \
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} \
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static inline __always_inline void \
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IOAPI_INLINE ( x86, outs ## _insn_suffix ) ( volatile _type *io_addr, \
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const _type *data, \
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unsigned int count ) { \
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unsigned int discard_S; \
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__asm__ __volatile__ ( "rep outs" #_insn_suffix \
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: "=S" ( discard_S ) \
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: "d" ( io_addr ), "c" ( count ), \
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"0" ( data ) ); \
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}
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X86_OUTX ( b, uint8_t, "b" );
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X86_OUTX ( w, uint16_t, "w" );
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X86_OUTX ( l, uint32_t, "k" );
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/*
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* Slow down I/O
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*
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*/
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static inline __always_inline void
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IOAPI_INLINE ( x86, iodelay ) ( void ) {
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__asm__ __volatile__ ( "outb %al, $0x80" );
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}
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/*
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* Memory barrier
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*
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*/
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static inline __always_inline void
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IOAPI_INLINE ( x86, mb ) ( void ) {
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__asm__ __volatile__ ( "lock; addl $0, 0(%%esp)" : : : "memory" );
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}
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#endif /* _IPXE_X86_IO_H */
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