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Merge from Etherboot 5.4

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This commit is contained in:
Michael Brown
2006-03-16 18:44:31 +00:00
parent 7e0a7a2e08 aeb70ec21c
commit 46e7bd5b52
2 changed files with 560 additions and 65 deletions
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114
src/drivers/net/smc9000.h
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@@ -109,6 +109,24 @@ typedef unsigned long int dword;
#define RPC_LED_RX (0x07) // LED = RX packet occurred
#define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
// Receive/Phy Control Register
/* BANK 0 */
#define RPC_REG 0x000A
#define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
#define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
#define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
#define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
#define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
#define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
#define RPC_LED_RES (0x01) // LED = Reserved
#define RPC_LED_10 (0x02) // LED = 10Mbps link detect
#define RPC_LED_FD (0x03) // LED = Full Duplex Mode
#define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
#define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
#define RPC_LED_TX (0x06) // LED = TX packet occurred
#define RPC_LED_RX (0x07) // LED = RX packet occurred
#define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
/* BANK 1 */
#define CONFIG 0
#define CFG_AUI_SELECT 0x100
@@ -210,6 +228,102 @@ typedef unsigned long int dword;
#define RS_MULTICAST 0x0001
#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
// Management Interface Register (MII)
#define MII_REG 0x0008
#define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
#define MII_MDOE 0x0008 // MII Output Enable
#define MII_MCLK 0x0004 // MII Clock, pin MDCLK
#define MII_MDI 0x0002 // MII Input, pin MDI
#define MII_MDO 0x0001 // MII Output, pin MDO
// PHY Register Addresses (LAN91C111 Internal PHY)
// PHY Control Register
#define PHY_CNTL_REG 0x00
#define PHY_CNTL_RST 0x8000 // 1=PHY Reset
#define PHY_CNTL_LPBK 0x4000 // 1=PHY Loopback
#define PHY_CNTL_SPEED 0x2000 // 1=100Mbps, 0=10Mpbs
#define PHY_CNTL_ANEG_EN 0x1000 // 1=Enable Auto negotiation
#define PHY_CNTL_PDN 0x0800 // 1=PHY Power Down mode
#define PHY_CNTL_MII_DIS 0x0400 // 1=MII 4 bit interface disabled
#define PHY_CNTL_ANEG_RST 0x0200 // 1=Reset Auto negotiate
#define PHY_CNTL_DPLX 0x0100 // 1=Full Duplex, 0=Half Duplex
#define PHY_CNTL_COLTST 0x0080 // 1= MII Colision Test
// PHY Status Register
#define PHY_STAT_REG 0x01
#define PHY_STAT_CAP_T4 0x8000 // 1=100Base-T4 capable
#define PHY_STAT_CAP_TXF 0x4000 // 1=100Base-X full duplex capable
#define PHY_STAT_CAP_TXH 0x2000 // 1=100Base-X half duplex capable
#define PHY_STAT_CAP_TF 0x1000 // 1=10Mbps full duplex capable
#define PHY_STAT_CAP_TH 0x0800 // 1=10Mbps half duplex capable
#define PHY_STAT_CAP_SUPR 0x0040 // 1=recv mgmt frames with not preamble
#define PHY_STAT_ANEG_ACK 0x0020 // 1=ANEG has completed
#define PHY_STAT_REM_FLT 0x0010 // 1=Remote Fault detected
#define PHY_STAT_CAP_ANEG 0x0008 // 1=Auto negotiate capable
#define PHY_STAT_LINK 0x0004 // 1=valid link
#define PHY_STAT_JAB 0x0002 // 1=10Mbps jabber condition
#define PHY_STAT_EXREG 0x0001 // 1=extended registers implemented
// PHY Identifier Registers
#define PHY_ID1_REG 0x02 // PHY Identifier 1
#define PHY_ID2_REG 0x03 // PHY Identifier 2
// PHY Auto-Negotiation Advertisement Register
#define PHY_AD_REG 0x04
#define PHY_AD_NP 0x8000 // 1=PHY requests exchange of Next Page
#define PHY_AD_ACK 0x4000 // 1=got link code word from remote
#define PHY_AD_RF 0x2000 // 1=advertise remote fault
#define PHY_AD_T4 0x0200 // 1=PHY is capable of 100Base-T4
#define PHY_AD_TX_FDX 0x0100 // 1=PHY is capable of 100Base-TX FDPLX
#define PHY_AD_TX_HDX 0x0080 // 1=PHY is capable of 100Base-TX HDPLX
#define PHY_AD_10_FDX 0x0040 // 1=PHY is capable of 10Base-T FDPLX
#define PHY_AD_10_HDX 0x0020 // 1=PHY is capable of 10Base-T HDPLX
#define PHY_AD_CSMA 0x0001 // 1=PHY is capable of 802.3 CMSA
// PHY Auto-negotiation Remote End Capability Register
#define PHY_RMT_REG 0x05
// Uses same bit definitions as PHY_AD_REG
// PHY Configuration Register 1
#define PHY_CFG1_REG 0x10
#define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
#define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
#define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
#define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
#define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
#define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
#define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
#define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
#define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
#define PHY_CFG1_TLVL_MASK 0x003C
#define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
// PHY Configuration Register 2
#define PHY_CFG2_REG 0x11
#define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
#define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
#define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
#define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
// PHY Status Output (and Interrupt status) Register
#define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
#define PHY_INT_INT 0x8000 // 1=bits have changed since last read
#define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
#define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
#define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
#define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
#define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
#define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
#define PHY_INT_JAB 0x0100 // 1=Jabber detected
#define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
#define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
// PHY Interrupt/Status Mask Register
#define PHY_MASK_REG 0x13 // Interrupt Mask
// Uses the same bit definitions as PHY_INT_REG
// PHY Register Addresses (LAN91C111 Internal PHY)