mirror of
https://github.com/ipxe/ipxe
synced 2026-06-29 00:07:28 +03:00
[tg3] Use updated DMA APIs
Replace malloc_phys with dma_alloc, free_phys with dma_free, alloc_iob with alloc_rx_iob, free_iob with free_rx_iob, virt_to_bus with dma or iob_dma. Replace dma_addr_t with physaddr_t. Signed-off-by: Joseph Wong <joseph.wong@broadcom.com>
This commit is contained in:
committed by
Michael Brown
parent
4906a255e3
commit
409747f42c
+55
-29
@@ -39,11 +39,13 @@ static void tg3_refill_prod_ring(struct tg3 *tp);
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#define TG3_RX_STD_RING_BYTES(tp) \
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(sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_MAX_SIZE_5700)
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void tg3_rx_prodring_fini(struct tg3_rx_prodring_set *tpr)
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void tg3_rx_prodring_fini(struct tg3 __unused *tp,
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struct tg3_rx_prodring_set *tpr)
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{ DBGP("%s\n", __func__);
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if (tpr->rx_std) {
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free_phys(tpr->rx_std, TG3_RX_STD_RING_BYTES(tp));
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dma_free(&tpr->rx_std_map, tpr->rx_std,
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TG3_RX_STD_RING_BYTES(tp));
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tpr->rx_std = NULL;
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}
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}
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@@ -56,7 +58,7 @@ static void tg3_free_consistent(struct tg3 *tp)
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{ DBGP("%s\n", __func__);
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if (tp->tx_ring) {
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free_phys(tp->tx_ring, TG3_TX_RING_BYTES);
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dma_free(&tp->tx_desc_map, tp->tx_ring, TG3_TX_RING_BYTES);
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tp->tx_ring = NULL;
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}
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@@ -64,16 +66,15 @@ static void tg3_free_consistent(struct tg3 *tp)
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tp->tx_buffers = NULL;
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if (tp->rx_rcb) {
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free_phys(tp->rx_rcb, TG3_RX_RCB_RING_BYTES(tp));
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tp->rx_rcb_mapping = 0;
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dma_free(&tp->rx_rcb_map, tp->rx_rcb,
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TG3_RX_RCB_RING_BYTES(tp));
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tp->rx_rcb = NULL;
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}
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tg3_rx_prodring_fini(&tp->prodring);
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tg3_rx_prodring_fini(tp, &tp->prodring);
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if (tp->hw_status) {
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free_phys(tp->hw_status, TG3_HW_STATUS_SIZE);
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tp->status_mapping = 0;
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dma_free(&tp->status_map, tp->hw_status, TG3_HW_STATUS_SIZE);
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tp->hw_status = NULL;
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}
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}
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@@ -88,32 +89,32 @@ int tg3_alloc_consistent(struct tg3 *tp)
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struct tg3_hw_status *sblk;
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struct tg3_rx_prodring_set *tpr = &tp->prodring;
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tp->hw_status = malloc_phys(TG3_HW_STATUS_SIZE, TG3_DMA_ALIGNMENT);
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tp->hw_status = dma_alloc(tp->dma, &tp->status_map,
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TG3_HW_STATUS_SIZE, TG3_DMA_ALIGNMENT);
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if (!tp->hw_status) {
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DBGC(tp->dev, "hw_status alloc failed\n");
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goto err_out;
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}
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tp->status_mapping = virt_to_bus(tp->hw_status);
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memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
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sblk = tp->hw_status;
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tpr->rx_std = malloc_phys(TG3_RX_STD_RING_BYTES(tp), TG3_DMA_ALIGNMENT);
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tpr->rx_std = dma_alloc(tp->dma, &tpr->rx_std_map,
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TG3_RX_STD_RING_BYTES(tp), TG3_DMA_ALIGNMENT);
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if (!tpr->rx_std) {
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DBGC(tp->dev, "rx prodring alloc failed\n");
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goto err_out;
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}
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tpr->rx_std_mapping = virt_to_bus(tpr->rx_std);
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memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
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tp->tx_buffers = zalloc(sizeof(struct ring_info) * TG3_TX_RING_SIZE);
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if (!tp->tx_buffers)
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goto err_out;
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tp->tx_ring = malloc_phys(TG3_TX_RING_BYTES, TG3_DMA_ALIGNMENT);
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tp->tx_ring = dma_alloc(tp->dma, &tp->tx_desc_map,
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TG3_TX_RING_BYTES, TG3_DMA_ALIGNMENT);
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if (!tp->tx_ring)
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goto err_out;
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tp->tx_desc_mapping = virt_to_bus(tp->tx_ring);
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/*
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* When RSS is enabled, the status block format changes
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@@ -124,10 +125,10 @@ int tg3_alloc_consistent(struct tg3 *tp)
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tp->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
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tp->rx_rcb = malloc_phys(TG3_RX_RCB_RING_BYTES(tp), TG3_DMA_ALIGNMENT);
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tp->rx_rcb = dma_alloc(tp->dma, &tp->rx_rcb_map,
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TG3_RX_RCB_RING_BYTES(tp), TG3_DMA_ALIGNMENT);
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if (!tp->rx_rcb)
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goto err_out;
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tp->rx_rcb_mapping = virt_to_bus(tp->rx_rcb);
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memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
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@@ -182,7 +183,11 @@ static void tg3_rx_iob_free(struct io_buffer *iobs[], int i)
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if (iobs[i] == NULL)
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return;
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free_iob(iobs[i]);
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/* RX iobufs were allocated via alloc_rx_iob() and are therefore
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* DMA-mapped through the platform DMA API; they must be released
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* via free_rx_iob() so the mapping is torn down.
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*/
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free_rx_iob(iobs[i]);
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iobs[i] = NULL;
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}
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@@ -302,7 +307,7 @@ static int tg3_transmit(struct net_device *dev, struct io_buffer *iob)
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struct tg3 *tp = dev->priv;
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u32 len, entry;
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dma_addr_t mapping;
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physaddr_t mapping;
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if (tg3_tx_avail(tp) < 1) {
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DBGC(dev, "Transmit ring full\n");
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@@ -312,7 +317,11 @@ static int tg3_transmit(struct net_device *dev, struct io_buffer *iob)
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entry = tp->tx_prod;
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iob_pad(iob, ETH_ZLEN);
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mapping = virt_to_bus(iob->data);
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/* The netdevice core has already called iob_map_tx() for this
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* iobuf (because netdev->dma is set), so iob_dma() returns the
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* platform-translated bus address suitable for the device.
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*/
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mapping = iob_dma(iob);
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len = iob_len(iob);
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tp->tx_buffers[entry].iob = iob;
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@@ -366,12 +375,13 @@ static void tg3_tx_complete(struct net_device *dev)
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* buffers the cpu only reads the last cacheline of the RX descriptor
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* (to fetch the error flags, vlan tag, checksum, and opaque cookie).
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*/
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static int tg3_alloc_rx_iob(struct tg3_rx_prodring_set *tpr, u32 dest_idx_unmasked)
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static int tg3_alloc_rx_iob(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
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u32 dest_idx_unmasked)
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{ DBGP("%s\n", __func__);
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struct tg3_rx_buffer_desc *desc;
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struct io_buffer *iob;
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dma_addr_t mapping;
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physaddr_t mapping;
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int dest_idx, iob_idx;
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dest_idx = dest_idx_unmasked & (TG3_RX_STD_MAX_SIZE_5700 - 1);
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@@ -382,15 +392,19 @@ static int tg3_alloc_rx_iob(struct tg3_rx_prodring_set *tpr, u32 dest_idx_unmask
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*
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* Callers depend upon this behavior and assume that
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* we leave everything unchanged if we fail.
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*
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* Allocate the receive iobuf already DMA-mapped through the
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* platform DMA API so the device may write into it under
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* preboot DMA protection (IOMMU).
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*/
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iob = alloc_iob(TG3_RX_STD_DMA_SZ);
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iob = alloc_rx_iob(TG3_RX_STD_DMA_SZ, tp->dma);
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if (iob == NULL)
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return -ENOMEM;
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iob_idx = dest_idx % TG3_DEF_RX_RING_PENDING;
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tpr->rx_iobufs[iob_idx] = iob;
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mapping = virt_to_bus(iob->data);
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mapping = iob_dma(iob);
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desc->addr_hi = ((u64)mapping >> 32);
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desc->addr_lo = ((u64)mapping & 0xffffffff);
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@@ -408,7 +422,7 @@ static void tg3_refill_prod_ring(struct tg3 *tp)
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while (tpr->rx_std_iob_cnt < TG3_DEF_RX_RING_PENDING) {
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if (tpr->rx_iobufs[idx % TG3_DEF_RX_RING_PENDING] == NULL) {
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if (tg3_alloc_rx_iob(tpr, idx) < 0) {
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if (tg3_alloc_rx_iob(tp, tpr, idx) < 0) {
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DBGC(tp->dev, "alloc_iob() failed for descriptor %d\n", idx);
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break;
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}
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@@ -532,22 +546,24 @@ static struct net_device_operations tg3_netdev_ops = {
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#define TEST_BUFFER_SIZE 0x2000
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int tg3_do_test_dma(struct tg3 *tp, u32 __unused *buf, dma_addr_t buf_dma, int size, int to_device);
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int tg3_do_test_dma(struct tg3 *tp, u32 __unused *buf, physaddr_t buf_dma, int size, int to_device);
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void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val);
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static int tg3_test_dma(struct tg3 *tp)
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{ DBGP("%s\n", __func__);
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dma_addr_t buf_dma;
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struct dma_mapping buf_map;
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physaddr_t buf_dma;
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u32 *buf;
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int ret = 0;
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buf = malloc_phys(TEST_BUFFER_SIZE, TG3_DMA_ALIGNMENT);
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memset(&buf_map, 0, sizeof(buf_map));
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buf = dma_alloc(tp->dma, &buf_map, TEST_BUFFER_SIZE, TG3_DMA_ALIGNMENT);
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if (!buf) {
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ret = -ENOMEM;
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goto out_nofree;
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}
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buf_dma = virt_to_bus(buf);
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buf_dma = dma(&buf_map, buf);
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DBGC2(tp->dev, "dma test buffer, virt: %p phys: %#016lx\n", buf, buf_dma);
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if (tg3_flag(tp, 57765_PLUS)) {
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@@ -709,7 +725,7 @@ static int tg3_test_dma(struct tg3 *tp)
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}
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out:
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free_phys(buf, TEST_BUFFER_SIZE);
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dma_free(&buf_map, buf, TEST_BUFFER_SIZE);
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out_nofree:
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return ret;
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}
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@@ -742,6 +758,16 @@ static int tg3_init_one(struct pci_device *pdev)
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tp->rx_mode = TG3_DEF_RX_MODE;
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tp->tx_mode = TG3_DEF_TX_MODE;
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/* Configure DMA. This must be done before any DMA allocation
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* (including the self-test buffer in tg3_test_dma) so that
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* buffers are mapped through the platform DMA implementation,
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* which is required when preboot DMA protection (IOMMU) is
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* active.
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*/
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tp->dma = &pdev->dma;
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dev->dma = tp->dma;
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dma_set_mask_64bit ( tp->dma );
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/* Subsystem IDs are required later */
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pci_read_config_word(tp->pdev, PCI_SUBSYSTEM_VENDOR_ID, &tp->subsystem_vendor);
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pci_read_config_word(tp->pdev, PCI_SUBSYSTEM_ID, &tp->subsystem_device);
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@@ -2809,8 +2809,6 @@ struct tg3_hw_stats {
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u8 __reserved4[0xb00-0x9c8];
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};
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typedef unsigned long dma_addr_t;
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/* 'mapping' is superfluous as the chip does not write into
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* the tx/rx post rings so we could just fetch it from there.
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* But the cache behavior is better how we are doing it now.
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@@ -2954,7 +2952,7 @@ struct tg3_rx_prodring_set {
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u32 rx_std_iob_cnt;
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struct tg3_rx_buffer_desc *rx_std;
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struct io_buffer *rx_iobufs[TG3_DEF_RX_RING_PENDING];
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dma_addr_t rx_std_mapping;
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struct dma_mapping rx_std_map;
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};
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#define TG3_IRQ_MAX_VECS_RSS 5
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@@ -3090,6 +3088,7 @@ struct tg3 {
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void *regs;
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struct net_device *dev;
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struct pci_device *pdev;
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struct dma_device *dma;
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u32 msg_enable;
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@@ -3125,9 +3124,9 @@ struct tg3 {
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struct tg3_tx_buffer_desc *tx_ring;
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struct ring_info *tx_buffers;
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dma_addr_t status_mapping;
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dma_addr_t rx_rcb_mapping;
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dma_addr_t tx_desc_mapping;
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struct dma_mapping status_map;
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struct dma_mapping rx_rcb_map;
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struct dma_mapping tx_desc_map;
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/* end tg3_napi */
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/* begin "everything else" cacheline(s) section */
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@@ -3371,7 +3370,7 @@ static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
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/* tg3_main.c forward declarations */
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int tg3_init_rings(struct tg3 *tp);
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void tg3_rx_prodring_fini(struct tg3_rx_prodring_set *tpr);
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void tg3_rx_prodring_fini(struct tg3 *tp, struct tg3_rx_prodring_set *tpr);
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///int tg3_rx_prodring_init(struct tg3 *tp, struct tg3_rx_prodring_set *tpr);
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/* tg3_phy.c forward declarations */
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@@ -3390,7 +3389,7 @@ int tg3_get_invariants(struct tg3 *tp);
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void tg3_init_bufmgr_config(struct tg3 *tp);
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int tg3_get_device_address(struct tg3 *tp);
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int tg3_halt(struct tg3 *tp);
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void tg3_set_txd(struct tg3 *tp, int entry, dma_addr_t mapping, int len, u32 flags);
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void tg3_set_txd(struct tg3 *tp, int entry, physaddr_t mapping, int len, u32 flags);
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void tg3_set_power_state_0(struct tg3 *tp);
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int tg3_alloc_consistent(struct tg3 *tp);
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int tg3_init_hw(struct tg3 *tp, int reset_phy);
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@@ -1765,7 +1765,7 @@ static void __tg3_set_coalesce(struct tg3 *tp)
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}
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static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
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dma_addr_t mapping, u32 maxlen_flags,
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physaddr_t mapping, u32 maxlen_flags,
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u32 nic_addr)
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{ DBGP("%s\n", __func__);
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@@ -1790,6 +1790,7 @@ static void tg3_rings_reset(struct tg3 *tp)
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int i;
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u32 txrcb, rxrcb, limit;
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physaddr_t status_dma;
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/* Disable all transmit rings but the first. */
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if (!tg3_flag(tp, 5705_PLUS))
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@@ -1844,14 +1845,20 @@ static void tg3_rings_reset(struct tg3 *tp)
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/* Clear status block in ram. */
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memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
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/* Set status block DMA address */
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/* Set status block DMA address. Use dma() so the platform DMA
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* implementation (e.g. EFI PCI_IO Map) can translate the host
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* virtual address into the bus address the device must use.
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*/
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status_dma = dma(&tp->status_map, tp->hw_status);
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tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
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((u64) tp->status_mapping >> 32));
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((u64) status_dma >> 32));
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tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
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((u64) tp->status_mapping & 0xffffffff));
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((u64) status_dma & 0xffffffff));
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if (tp->tx_ring) {
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tg3_set_bdinfo(tp, txrcb, tp->tx_desc_mapping,
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tg3_set_bdinfo(tp, txrcb,
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dma(&tp->tx_desc_map, tp->tx_ring),
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(TG3_TX_RING_SIZE <<
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BDINFO_FLAGS_MAXLEN_SHIFT),
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NIC_SRAM_TX_BUFFER_DESC);
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@@ -1860,7 +1867,8 @@ static void tg3_rings_reset(struct tg3 *tp)
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/* FIXME: will TG3_RX_RET_MAX_SIZE_5705 work on all cards? */
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if (tp->rx_rcb) {
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tg3_set_bdinfo(tp, rxrcb, tp->rx_rcb_mapping,
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tg3_set_bdinfo(tp, rxrcb,
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dma(&tp->rx_rcb_map, tp->rx_rcb),
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TG3_RX_RET_MAX_SIZE_5705 <<
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BDINFO_FLAGS_MAXLEN_SHIFT, 0);
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rxrcb += TG3_BDINFO_SIZE;
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@@ -1900,6 +1908,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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u32 val, rdmac_mode;
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int i, err, limit;
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struct tg3_rx_prodring_set *tpr = &tp->prodring;
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physaddr_t rx_std_dma;
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tg3_stop_fw(tp);
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@@ -2123,10 +2132,13 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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* The size of each ring is fixed in the firmware, but the location is
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* configurable.
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*/
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rx_std_dma = dma(&tpr->rx_std_map, tpr->rx_std);
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tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
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((u64) tpr->rx_std_mapping >> 32));
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((u64) rx_std_dma >> 32));
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tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
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((u64) tpr->rx_std_mapping & 0xffffffff));
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((u64) rx_std_dma & 0xffffffff));
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if (!tg3_flag(tp, 5717_PLUS))
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tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
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NIC_SRAM_RX_BUFFER_DESC);
|
||||
@@ -2581,7 +2593,7 @@ int tg3_init_hw(struct tg3 *tp, int reset_phy)
|
||||
}
|
||||
|
||||
void tg3_set_txd(struct tg3 *tp, int entry,
|
||||
dma_addr_t mapping, int len, u32 flags)
|
||||
physaddr_t mapping, int len, u32 flags)
|
||||
{ DBGP("%s\n", __func__);
|
||||
|
||||
struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
|
||||
@@ -2592,7 +2604,7 @@ void tg3_set_txd(struct tg3 *tp, int entry,
|
||||
txd->vlan_tag = 0;
|
||||
}
|
||||
|
||||
int tg3_do_test_dma(struct tg3 *tp, u32 __unused *buf, dma_addr_t buf_dma, int size, int to_device)
|
||||
int tg3_do_test_dma(struct tg3 *tp, u32 __unused *buf, physaddr_t buf_dma, int size, int to_device)
|
||||
{ DBGP("%s\n", __func__);
|
||||
|
||||
struct tg3_internal_buffer_desc test_desc;
|
||||
|
||||
Reference in New Issue
Block a user