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[riscv] Use load and store pseudo-instructions where possible

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The pattern of "load address to register" followed by "load value from
address in register" generally results in three instructions: two to
load the address and one to load the value.

This can be reduced to two instructions by allowing the assembler to
incorporate the low bits of the address within the load (or store)
instruction itself.  In the case of a store, this requires specifying
a second register that can be temporarily used to hold the high bits
of the address.  (In the case of a load, the destination register is
reused for this purpose.)

Signed-off-by: Michael Brown <mcb30@ipxe.org>
This commit is contained in:
Michael Brown
2025-05-09 15:02:47 +01:00
parent 134d76379e
commit 3027864f13
2 changed files with 5 additions and 10 deletions
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12
src/arch/riscv/prefix/libprefix.S
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@@ -257,8 +257,7 @@ apply_relocs:
la a2, _edata
/* Calculate relocation addend */
la t0, prefix_virt
LOADN a0, (t0)
LOADN a0, prefix_virt
sub a0, a1, a0
/* Skip applying relocations if addend is zero */
@@ -523,8 +522,7 @@ enable_paging_64:
li a1, SATP_MODE_SV57
/* Calculate virtual address offset */
la t0, prefix_virt
LOADN t0, (t0)
LOADN t0, prefix_virt
la t1, _prefix
sub a0, t1, t0
@@ -567,8 +565,7 @@ enable_paging_64_loop:
STOREN t0, -PTE_SIZE(a4)
/* Calculate PTE[x] address for iPXE virtual address map */
la t0, prefix_virt
LOADN t0, (t0)
LOADN t0, prefix_virt
srli t0, t0, VPN1_LSB
andi t0, t0, ( PTE_COUNT - 1 )
slli t0, t0, PTE_SIZE_LOG2
@@ -711,8 +708,7 @@ enable_paging_32:
mv a2, a0
/* Calculate virtual address offset */
la t0, prefix_virt
LOADN t0, (t0)
LOADN t0, prefix_virt
la t1, _prefix
sub a0, t1, t0