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[realtek] Replace driver for Realtek Gigabit NICs
Tested-by: Thomas Miletich <thomas.miletich@gmail.com> Debugged-by: Thomas Miletich <thomas.miletich@gmail.com> Tested-by: Robin Smidsrød <robin@smidsrod.no> Signed-off-by: Michael Brown <mcb30@ipxe.org>
This commit is contained in:
Michael Brown
205
src/drivers/net/realtek.h
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205
src/drivers/net/realtek.h
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#ifndef _REALTEK_H
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#define _REALTEK_H
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/** @file
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*
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* Realtek 10/100/1000 network card driver
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*
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*/
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FILE_LICENCE ( GPL2_OR_LATER );
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#include <ipxe/spi.h>
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#include <ipxe/spi_bit.h>
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#include <ipxe/nvo.h>
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#include <ipxe/if_ether.h>
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/** PCI memory BAR size */
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#define RTL_BAR_SIZE 0x100
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/** A packet descriptor */
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struct realtek_descriptor {
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/** Buffer size */
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uint16_t length;
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/** Flags */
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uint16_t flags;
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/** Reserved */
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uint32_t reserved;
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/** Buffer address */
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uint64_t address;
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} __attribute__ (( packed ));
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/** Descriptor buffer size mask */
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#define RTL_DESC_SIZE_MASK 0x3fff
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/** Packet descriptor flags */
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enum realtek_descriptor_flags {
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/** Descriptor is owned by NIC */
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RTL_DESC_OWN = 0x8000,
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/** End of descriptor ring */
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RTL_DESC_EOR = 0x4000,
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/** First segment descriptor */
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RTL_DESC_FS = 0x2000,
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/** Last segment descriptor */
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RTL_DESC_LS = 0x1000,
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/** Receive error summary */
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RTL_DESC_RES = 0x0020,
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};
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/** Descriptor ring alignment */
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#define RTL_RING_ALIGN 256
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/** ID Register 0 (6 bytes) */
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#define RTL_IDR0 0x00
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/** Multicast Register 0 (dword) */
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#define RTL_MAR0 0x08
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/** Multicast Register 4 (dword) */
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#define RTL_MAR4 0x0c
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/** Transmit Normal Priority Descriptors (qword) */
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#define RTL_TNPDS 0x20
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/** Number of transmit descriptors */
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#define RTL_NUM_TX_DESC 4
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/** Command Register (byte) */
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#define RTL_CR 0x37
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#define RTL_CR_RST 0x10 /**< Reset */
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#define RTL_CR_RE 0x08 /**< Receiver Enable */
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#define RTL_CR_TE 0x04 /**< Transmit Enable */
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/** Maximum time to wait for a reset, in milliseconds */
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#define RTL_RESET_MAX_WAIT_MS 100
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/** Transmit Priority Polling Register (byte) */
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#define RTL_TPPOLL 0x38
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#define RTL_TPPOLL_NPQ 0x40 /**< Normal Priority Queue Polling */
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/** Interrupt Mask Register (word) */
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#define RTL_IMR 0x3c
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#define RTL_IRQ_PUN_LINKCHG 0x20 /**< Packet underrun / link change */
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#define RTL_IRQ_TER 0x08 /**< Transmit error */
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#define RTL_IRQ_TOK 0x04 /**< Transmit OK */
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#define RTL_IRQ_RER 0x02 /**< Receive error */
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#define RTL_IRQ_ROK 0x01 /**< Receive OK */
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/** Interrupt Status Register (word) */
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#define RTL_ISR 0x3e
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/** Receive (Rx) Configuration Register (dword) */
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#define RTL_RCR 0x44
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#define RTL_RCR_9356SEL 0x40 /**< EEPROM is a 93C56 */
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#define RTL_RCR_AB 0x08 /**< Accept broadcast packets */
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#define RTL_RCR_AM 0x04 /**< Accept multicast packets */
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#define RTL_RCR_APM 0x02 /**< Accept physical match packets */
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#define RTL_RCR_AAP 0x01 /**< Accept all packets */
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/** 93C46 (93C56) Command Register (byte) */
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#define RTL_9346CR 0x50
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#define RTL_9346CR_EEM1 0x80 /**< Mode select bit 1 */
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#define RTL_9346CR_EEM0 0x40 /**< Mode select bit 0 */
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#define RTL_9346CR_EECS 0x08 /**< Chip select */
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#define RTL_9346CR_EESK 0x04 /**< Clock */
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#define RTL_9346CR_EEDI 0x02 /**< Data in */
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#define RTL_9346CR_EEDO 0x01 /**< Data out */
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/** Word offset of MAC address within EEPROM */
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#define RTL_EEPROM_MAC ( 0x0e / 2 )
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/** Word offset of VPD / non-volatile options within EEPROM */
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#define RTL_EEPROM_VPD ( 0x40 / 2 )
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/** Length of VPD / non-volatile options within EEPROM */
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#define RTL_EEPROM_VPD_LEN 0x40
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/** Configuration Register 1 (byte) */
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#define RTL_CONFIG1 0x52
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#define RTL_CONFIG1_VPD 0x02 /**< Vital Product Data enabled */
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/** PHY Access Register (dword) */
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#define RTL_PHYAR 0x60
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#define RTL_PHYAR_FLAG 0x80000000UL /**< Read/write flag */
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/** Construct PHY Access Register value */
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#define RTL_PHYAR_VALUE( flag, reg, data ) ( (flag) | ( (reg) << 16 ) | (data) )
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/** Extract PHY Access Register data */
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#define RTL_PHYAR_DATA( value ) ( (value) & 0xffff )
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/** Maximum time to wait for PHY access, in microseconds */
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#define RTL_MII_MAX_WAIT_US 500
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/** PHY (GMII, MII, or TBI) Status Register (byte) */
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#define RTL_PHYSTATUS 0x6c
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#define RTL_PHYSTATUS_LINKSTS 0x02 /**< Link ok */
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/** RX Packet Maximum Size Register (word) */
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#define RTL_RMS 0xda
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/** C+ Command Register (word) */
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#define RTL_CPCR 0xe0
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#define RTL_CPCR_DAC 0x10 /**< PCI Dual Address Cycle Enable */
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#define RTL_CPCR_MULRW 0x08 /**< PCI Multiple Read/Write Enable */
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/** Receive Descriptor Start Address Register (qword) */
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#define RTL_RDSAR 0xe4
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/** Number of receive descriptors */
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#define RTL_NUM_RX_DESC 4
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/** Receive buffer length */
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#define RTL_RX_MAX_LEN ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ )
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/** A Realtek descriptor ring */
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struct realtek_ring {
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/** Descriptors */
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struct realtek_descriptor *desc;
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/** Producer index */
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unsigned int prod;
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/** Consumer index */
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unsigned int cons;
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/** Descriptor start address register */
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unsigned int reg;
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/** Length (in bytes) */
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size_t len;
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};
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/**
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* Initialise descriptor ring
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*
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* @v ring Descriptor ring
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* @v count Number of descriptors
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* @v reg Descriptor start address register
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*/
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static inline __attribute__ (( always_inline)) void
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realtek_init_ring ( struct realtek_ring *ring, unsigned int count,
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unsigned int reg ) {
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ring->len = ( count * sizeof ( ring->desc[0] ) );
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ring->reg = reg;
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}
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/** A Realtek network card */
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struct realtek_nic {
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/** Registers */
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void *regs;
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/** SPI bit-bashing interface */
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struct spi_bit_basher spibit;
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/** EEPROM */
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struct spi_device eeprom;
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/** Non-volatile options */
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struct nvo_block nvo;
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/** MII interface */
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struct mii_interface mii;
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/** Transmit descriptor ring */
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struct realtek_ring tx;
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/** Receive descriptor ring */
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struct realtek_ring rx;
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/** Receive I/O buffers */
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struct io_buffer *rx_iobuf[RTL_NUM_RX_DESC];
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};
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#endif /* _REALTEK_H */
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