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https://github.com/ipxe/ipxe
synced 2026-05-10 18:10:36 +03:00
Warnings purge of drivers (continued)
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@@ -22,12 +22,14 @@
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#include "bnx2.h"
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#include "bnx2_fw.h"
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#if 0
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/* Dummy defines for error handling */
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#define EBUSY 1
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#define ENODEV 2
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#define EINVAL 3
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#define ENOMEM 4
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#define EIO 5
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#endif
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/* The bnx2 seems to be picky about the alignment of the receive buffers
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* and possibly the status block.
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@@ -1165,7 +1167,7 @@ bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
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/* If we timed out, inform the firmware that this is the case. */
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if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
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if (!silent)
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printf("fw sync timeout, reset code = %x\n", msg_data);
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printf("fw sync timeout, reset code = %x\n", (unsigned int) msg_data);
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msg_data &= ~BNX2_DRV_MSG_CODE;
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msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
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@@ -2033,7 +2035,7 @@ static void
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bnx2_init_rx_ring(struct bnx2 *bp)
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{
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struct rx_bd *rxbd;
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int i;
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unsigned int i;
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u16 prod, ring_prod;
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u32 val;
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@@ -2066,7 +2068,7 @@ bnx2_init_rx_ring(struct bnx2 *bp)
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val = bp->rx_desc_mapping & 0xffffffff;
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CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
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for (i = 0; i < bp->rx_ring_size; i++) {
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for (i = 0; (int) i < bp->rx_ring_size; i++) {
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rxbd = &bp->rx_desc_ring[RX_RING_IDX(ring_prod)];
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rxbd->rx_bd_haddr_hi = 0;
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rxbd->rx_bd_haddr_lo = virt_to_bus(&bnx2_bss.rx_buf[ring_prod][0]);
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@@ -2635,8 +2637,8 @@ bnx2_probe(struct nic *nic, struct pci_device *pdev)
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memcpy(nic->node_addr, bp->mac_addr, ETH_ALEN);
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printf("Ethernet addr: %s\n", eth_ntoa( nic->node_addr ) );
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printf("Broadcom NetXtreme II (%c%d) PCI%s %s %dMHz\n",
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((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
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((CHIP_ID(bp) & 0x0ff0) >> 4),
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(int) ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
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(int) ((CHIP_ID(bp) & 0x0ff0) >> 4),
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((bp->flags & PCIX_FLAG) ? "-X" : ""),
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((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
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bp->bus_speed_mhz);
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