mirror of
https://github.com/ipxe/ipxe
synced 2025-12-24 06:22:59 +03:00
[timer] Formalise the timer API
We now have two implementations for the timer API: one using the time-of-day counter at 40:70 and one using RDTSC. Both make use of timer2_udelay().
This commit is contained in:
@@ -497,7 +497,7 @@ a3c90x_transmit(struct nic *nic __unused, const char *d, unsigned int t,
|
||||
|
||||
unsigned char status;
|
||||
unsigned i, retries;
|
||||
tick_t ct;
|
||||
unsigned long ct;
|
||||
|
||||
for (retries=0; retries < XMIT_RETRIES ; retries++)
|
||||
{
|
||||
@@ -543,7 +543,7 @@ a3c90x_transmit(struct nic *nic __unused, const char *d, unsigned int t,
|
||||
ct = currticks();
|
||||
|
||||
while (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w)&0x0004) &&
|
||||
ct + 10*USECS_IN_MSEC < currticks());
|
||||
ct + 10*1000 < currticks());
|
||||
;
|
||||
|
||||
if (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w)&0x0004))
|
||||
|
||||
@@ -407,7 +407,7 @@ static void eepro100_transmit(struct nic *nic, const char *d, unsigned int t, un
|
||||
} hdr;
|
||||
unsigned short status;
|
||||
int s1, s2;
|
||||
tick_t ct;
|
||||
unsigned long ct;
|
||||
|
||||
status = inw(ioaddr + SCBStatus);
|
||||
/* Acknowledge all of the current interrupt sources ASAP. */
|
||||
@@ -448,7 +448,7 @@ static void eepro100_transmit(struct nic *nic, const char *d, unsigned int t, un
|
||||
|
||||
ct = currticks();
|
||||
/* timeout 10 ms for transmit */
|
||||
while (!txfd.status && ct + 10*USECS_IN_MSEC)
|
||||
while (!txfd.status && ct + 10*1000)
|
||||
/* Wait */;
|
||||
s2 = inw (ioaddr + SCBStatus);
|
||||
|
||||
@@ -608,7 +608,7 @@ static int eepro100_probe ( struct nic *nic, struct pci_device *pci ) {
|
||||
int read_cmd, ee_size;
|
||||
int options;
|
||||
int rx_mode;
|
||||
tick_t ct;
|
||||
unsigned long ct;
|
||||
|
||||
/* we cache only the first few words of the EEPROM data
|
||||
be careful not to access beyond this array */
|
||||
@@ -753,7 +753,7 @@ static int eepro100_probe ( struct nic *nic, struct pci_device *pci ) {
|
||||
whereami ("started TX thingy (config, iasetup).");
|
||||
|
||||
ct = currticks();
|
||||
while (!txfd.status && ct + 10*USECS_IN_MSEC < currticks())
|
||||
while (!txfd.status && ct + 10*1000 < currticks())
|
||||
/* Wait */;
|
||||
|
||||
/* Read the status register once to disgard stale data */
|
||||
|
||||
@@ -309,7 +309,7 @@ epic100_transmit(struct nic *nic, const char *destaddr, unsigned int type,
|
||||
unsigned short nstype;
|
||||
unsigned char *txp;
|
||||
int entry;
|
||||
tick_t ct;
|
||||
unsigned long ct;
|
||||
|
||||
/* Calculate the next Tx descriptor entry. */
|
||||
entry = cur_tx % TX_RING_SIZE;
|
||||
@@ -352,7 +352,7 @@ epic100_transmit(struct nic *nic, const char *destaddr, unsigned int type,
|
||||
ct = currticks();
|
||||
/* timeout 10 ms for transmit */
|
||||
while ((le32_to_cpu(tx_ring[entry].status) & (TRING_OWN)) &&
|
||||
ct + 10*USECS_IN_MSEC < currticks())
|
||||
ct + 10*1000 < currticks())
|
||||
/* Wait */;
|
||||
|
||||
if ((le32_to_cpu(tx_ring[entry].status) & TRING_OWN) != 0)
|
||||
|
||||
@@ -784,7 +784,7 @@ ReadMII (int byMIIIndex, int ioaddr)
|
||||
char byMIIAdrbak;
|
||||
char byMIICRbak;
|
||||
char byMIItemp;
|
||||
tick_t ct;
|
||||
unsigned long ct;
|
||||
|
||||
byMIIAdrbak = inb (byMIIAD);
|
||||
byMIICRbak = inb (byMIICR);
|
||||
@@ -800,7 +800,7 @@ ReadMII (int byMIIIndex, int ioaddr)
|
||||
byMIItemp = byMIItemp & 0x40;
|
||||
|
||||
ct = currticks();
|
||||
while (byMIItemp != 0 && ct + 2*USECS_IN_MSEC < currticks())
|
||||
while (byMIItemp != 0 && ct + 2*1000 < currticks())
|
||||
{
|
||||
byMIItemp = inb (byMIICR);
|
||||
byMIItemp = byMIItemp & 0x40;
|
||||
@@ -825,7 +825,7 @@ WriteMII (char byMIISetByte, char byMIISetBit, char byMIIOP, int ioaddr)
|
||||
char byMIIAdrbak;
|
||||
char byMIICRbak;
|
||||
char byMIItemp;
|
||||
tick_t ct;
|
||||
unsigned long ct;
|
||||
|
||||
|
||||
byMIIAdrbak = inb (byMIIAD);
|
||||
@@ -842,7 +842,7 @@ WriteMII (char byMIISetByte, char byMIISetBit, char byMIIOP, int ioaddr)
|
||||
byMIItemp = byMIItemp & 0x40;
|
||||
|
||||
ct = currticks();
|
||||
while (byMIItemp != 0 && ct + 2*USECS_IN_MSEC < currticks())
|
||||
while (byMIItemp != 0 && ct + 2*1000 < currticks())
|
||||
{
|
||||
byMIItemp = inb (byMIICR);
|
||||
byMIItemp = byMIItemp & 0x40;
|
||||
@@ -872,7 +872,7 @@ WriteMII (char byMIISetByte, char byMIISetBit, char byMIIOP, int ioaddr)
|
||||
byMIItemp = byMIItemp & 0x20;
|
||||
|
||||
ct = currticks();
|
||||
while (byMIItemp != 0 && ct + 2*USECS_IN_MSEC < currticks())
|
||||
while (byMIItemp != 0 && ct + 2*1000 < currticks())
|
||||
{
|
||||
byMIItemp = inb (byMIICR);
|
||||
byMIItemp = byMIItemp & 0x20;
|
||||
@@ -1346,7 +1346,7 @@ rhine_transmit (struct nic *nic,
|
||||
unsigned char CR1bak;
|
||||
unsigned char CR0bak;
|
||||
unsigned int nstype;
|
||||
tick_t ct;
|
||||
unsigned long ct;
|
||||
|
||||
|
||||
/*printf ("rhine_transmit\n"); */
|
||||
@@ -1390,7 +1390,7 @@ rhine_transmit (struct nic *nic,
|
||||
ct = currticks();
|
||||
/* Wait until transmit is finished or timeout*/
|
||||
while((tp->tx_ring[entry].tx_status.bits.own_bit !=0) &&
|
||||
ct + 10*USECS_IN_MSEC < currticks())
|
||||
ct + 10*1000 < currticks())
|
||||
;
|
||||
|
||||
if(tp->tx_ring[entry].tx_status.bits.terr == 0)
|
||||
|
||||
@@ -112,7 +112,7 @@ static const char *w89c840_version = "driver Version 0.94 - December 12, 2003";
|
||||
|
||||
/* Operational parameters that usually are not changed. */
|
||||
/* Time in jiffies before concluding the transmitter is hung. */
|
||||
#define TX_TIMEOUT (10*USECS_IN_MSEC)
|
||||
#define TX_TIMEOUT (10*1000)
|
||||
|
||||
#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
|
||||
|
||||
@@ -486,7 +486,7 @@ static void w89c840_transmit(
|
||||
/* send the packet to destination */
|
||||
unsigned entry;
|
||||
int transmit_status;
|
||||
tick_t ct;
|
||||
unsigned long ct;
|
||||
|
||||
/* Caution: the write order is important here, set the field
|
||||
with the "ownership" bits last. */
|
||||
|
||||
Reference in New Issue
Block a user