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https://github.com/ipxe/ipxe
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Restructured PCI subsystem to fit the new device model.
Generic PCI code now handles 64-bit BARs correctly when setting "membase"; drivers should need to call pci_bar_start() only if they want to use BARs other than the first memory or I/O BAR. Split rarely-used PCI functions out into pciextra.c. Core PCI code is now 662 bytes (down from 1308 bytes in Etherboot 5.4). 284 bytes of this saving comes from the pci/pciextra split. Cosmetic changes to lots of drivers (e.g. vendor_id->vendor in order to match the names used in Linux).
This commit is contained in:
Michael Brown
@@ -1,367 +1,339 @@
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#include "stdint.h"
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#include "string.h"
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#include "console.h"
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#include "nic.h"
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/*
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* Copyright (C) 2006 Michael Brown <mbrown@fensystems.co.uk>.
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*
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* Based in part on pci.c from Etherboot 5.4, by Ken Yap and David
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* Munro, in turn based on the Linux kernel's PCI implementation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <stdint.h>
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#include <string.h>
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#include <errno.h>
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#include <malloc.h>
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#include <gpxe/tables.h>
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#include <gpxe/device.h>
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#include <gpxe/pci.h>
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/*
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* pci_io.c may know how many buses we have, in which case it can
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* overwrite this value.
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/** @file
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*
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* PCI bus
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*
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*/
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static struct pci_driver pci_drivers[0] __table_start ( pci_drivers );
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static struct pci_driver pci_drivers_end[0] __table_end ( pci_drivers );
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static void pcibus_remove ( struct root_device *rootdev );
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/**
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* Maximum PCI bus number
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*
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* Architecture-specific code may know how many buses we have, in
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* which case it can overwrite this value.
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*
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*/
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unsigned int pci_max_bus = 0xff;
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/*
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* Increment a bus_loc structure to the next possible PCI location.
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* Leave the structure zeroed and return 0 if there are no more valid
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* locations.
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/**
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* Read PCI BAR
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*
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* @v pci PCI device
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* @v reg PCI register number
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* @ret bar Base address register
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*
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* Reads the specified PCI base address register, including the flags
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* portion. 64-bit BARs will be handled automatically. If the value
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* of the 64-bit BAR exceeds the size of an unsigned long (i.e. if the
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* high dword is non-zero on a 32-bit platform), then the value
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* returned will be zero plus the flags for a 64-bit BAR. Unreachable
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* 64-bit BARs are therefore returned as uninitialised 64-bit BARs.
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*/
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static int pci_next_location ( struct bus_loc *bus_loc ) {
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struct pci_loc *pci_loc = ( struct pci_loc * ) bus_loc;
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/*
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* Ensure that there is sufficient space in the shared bus
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* structures for a struct pci_loc and a struct
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* pci_dev, as mandated by bus.h.
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*
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*/
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BUS_LOC_CHECK ( struct pci_loc );
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BUS_DEV_CHECK ( struct pci_device );
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static unsigned long pci_bar ( struct pci_device *pci, unsigned int reg ) {
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uint32_t low;
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uint32_t high;
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return ( ++pci_loc->busdevfn );
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}
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/*
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* Fill in parameters (vendor & device ids, class, membase etc.) for a
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* PCI device based on bus & devfn.
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*
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* Returns 1 if a device was found, 0 for no device present.
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*
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*/
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static int pci_fill_device ( struct bus_dev *bus_dev,
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struct bus_loc *bus_loc ) {
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struct pci_loc *pci_loc = ( struct pci_loc * ) bus_loc;
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struct pci_device *pci = ( struct pci_device * ) bus_dev;
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uint16_t busdevfn = pci_loc->busdevfn;
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static struct {
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uint16_t busdevfn0;
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int is_present;
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} cache = { 0, 1 };
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uint32_t l;
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int reg;
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/* Store busdevfn in struct pci_device and set default values */
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pci->busdevfn = busdevfn;
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pci->name = "?";
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/* Check bus is within range */
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if ( PCI_BUS ( busdevfn ) > pci_max_bus ) {
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return 0;
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}
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/* Check to see if we've cached the result that this is a
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* non-zero function on a non-existent card. This is done to
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* increase scan speed by a factor of 8.
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*/
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if ( ( PCI_FUNC ( busdevfn ) != 0 ) &&
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( PCI_FN0 ( busdevfn ) == cache.busdevfn0 ) &&
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( ! cache.is_present ) ) {
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return 0;
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}
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/* Check to see if there's anything physically present.
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*/
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pci_read_config_dword ( pci, PCI_VENDOR_ID, &l );
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/* some broken boards return 0 if a slot is empty: */
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if ( ( l == 0xffffffff ) || ( l == 0x00000000 ) ) {
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if ( PCI_FUNC ( busdevfn ) == 0 ) {
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/* Don't look for subsequent functions if the
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* card itself is not present.
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*/
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cache.busdevfn0 = busdevfn;
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cache.is_present = 0;
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}
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return 0;
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}
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pci->vendor_id = l & 0xffff;
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pci->device_id = ( l >> 16 ) & 0xffff;
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/* Check that we're not a duplicate function on a
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* non-multifunction device.
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*/
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if ( PCI_FUNC ( busdevfn ) != 0 ) {
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uint8_t header_type;
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pci->busdevfn &= PCI_FN0 ( busdevfn );
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pci_read_config_byte ( pci, PCI_HEADER_TYPE, &header_type );
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pci->busdevfn = busdevfn;
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if ( ! ( header_type & 0x80 ) ) {
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return 0;
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}
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}
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/* Get device class */
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pci_read_config_word ( pci, PCI_SUBCLASS_CODE, &pci->class );
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/* Get revision */
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pci_read_config_byte ( pci, PCI_REVISION, &pci->revision );
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/* Get the "membase" */
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pci_read_config_dword ( pci, PCI_BASE_ADDRESS_1, &pci->membase );
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/* Get the "ioaddr" */
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pci->ioaddr = 0;
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for ( reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4 ) {
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pci_read_config_dword ( pci, reg, &pci->ioaddr );
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if ( pci->ioaddr & PCI_BASE_ADDRESS_SPACE_IO ) {
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pci->ioaddr &= PCI_BASE_ADDRESS_IO_MASK;
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if ( pci->ioaddr ) {
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break;
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pci_read_config_dword ( pci, reg, &low );
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if ( ( low & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK) )
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== (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64) ){
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pci_read_config_dword ( pci, reg + 4, &high );
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if ( high ) {
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if ( sizeof ( unsigned long ) > sizeof ( uint32_t ) ) {
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return ( ( ( uint64_t ) high << 32 ) | low );
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} else {
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DBG ( "Unhandled 64-bit BAR %08x%08x\n",
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high, low );
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return PCI_BASE_ADDRESS_MEM_TYPE_64;
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}
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}
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pci->ioaddr = 0;
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}
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/* Get the irq */
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pci_read_config_byte ( pci, PCI_INTERRUPT_PIN, &pci->irq );
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if ( pci->irq ) {
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pci_read_config_byte ( pci, PCI_INTERRUPT_LINE, &pci->irq );
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}
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DBG ( "PCI found device %hhx:%hhx.%d Class %hx: %hx:%hx (rev %hhx)\n",
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PCI_BUS ( pci->busdevfn ), PCI_DEV ( pci->busdevfn ),
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PCI_FUNC ( pci->busdevfn ), pci->class, pci->vendor_id,
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pci->device_id, pci->revision );
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return 1;
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return low;
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}
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/*
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* Test whether or not a driver is capable of driving the device.
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/**
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* Find the start of a PCI BAR
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*
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* @v pci PCI device
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* @v reg PCI register number
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* @ret start BAR start address
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*
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* Reads the specified PCI base address register, and returns the
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* address portion of the BAR (i.e. without the flags).
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*
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* If the address exceeds the size of an unsigned long (i.e. if a
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* 64-bit BAR has a non-zero high dword on a 32-bit machine), the
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* return value will be zero.
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*/
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static int pci_check_driver ( struct bus_dev *bus_dev,
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struct device_driver *device_driver ) {
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struct pci_device *pci = ( struct pci_device * ) bus_dev;
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struct pci_driver *pci_driver
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= ( struct pci_driver * ) device_driver->bus_driver_info;
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unsigned int i;
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unsigned long pci_bar_start ( struct pci_device *pci, unsigned int reg ) {
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unsigned long bar;
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/* If driver has a class, and class matches, use it */
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if ( pci_driver->class &&
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( pci_driver->class == pci->class ) ) {
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DBG ( "PCI driver %s matches class %hx\n",
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device_driver->name, pci_driver->class );
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pci->name = device_driver->name;
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return 1;
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bar = pci_bar ( pci, reg );
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if ( (bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY ){
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return ( bar & PCI_BASE_ADDRESS_MEM_MASK );
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} else {
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return ( bar & PCI_BASE_ADDRESS_IO_MASK );
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}
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/* If any of driver's IDs match, use it */
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for ( i = 0 ; i < pci_driver->id_count; i++ ) {
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struct pci_id *id = &pci_driver->ids[i];
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if ( ( pci->vendor_id == id->vendor_id ) &&
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( pci->device_id == id->device_id ) ) {
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DBG ( "PCI driver %s device %s matches ID %hx:%hx\n",
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device_driver->name, id->name,
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id->vendor_id, id->device_id );
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pci->name = id->name;
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return 1;
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}
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/**
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* Read membase and ioaddr for a PCI device
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*
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* @v pci PCI device
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*
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* This scans through all PCI BARs on the specified device. The first
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* valid memory BAR is recorded as pci_device::membase, and the first
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* valid IO BAR is recorded as pci_device::ioaddr.
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*
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* 64-bit BARs are handled automatically. On a 32-bit platform, if a
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* 64-bit BAR has a non-zero high dword, it will be regarded as
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* invalid.
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*/
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static void pci_read_bases ( struct pci_device *pci ) {
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unsigned long bar;
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int reg;
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for ( reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4 ) {
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bar = pci_bar ( pci, reg );
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if ( bar & PCI_BASE_ADDRESS_SPACE_IO ) {
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if ( ! pci->ioaddr )
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pci->ioaddr =
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( bar & PCI_BASE_ADDRESS_IO_MASK );
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} else {
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if ( ! pci->membase )
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pci->membase =
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( bar & PCI_BASE_ADDRESS_MEM_MASK );
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/* Skip next BAR if 64-bit */
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if ( bar & PCI_BASE_ADDRESS_MEM_TYPE_64 )
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reg += 4;
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}
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}
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return 0;
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}
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/*
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* Describe a PCI device
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/**
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* Enable PCI device
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*
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*/
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static char * pci_describe_device ( struct bus_dev *bus_dev ) {
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struct pci_device *pci = ( struct pci_device * ) bus_dev;
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static char pci_description[] = "PCI 00:00.0";
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sprintf ( pci_description + 4, "%hhx:%hhx.%d",
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PCI_BUS ( pci->busdevfn ), PCI_DEV ( pci->busdevfn ),
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PCI_FUNC ( pci->busdevfn ) );
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return pci_description;
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}
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/*
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* Name a PCI device
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* @v pci PCI device
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*
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*/
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static const char * pci_name_device ( struct bus_dev *bus_dev ) {
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struct pci_device *pci = ( struct pci_device * ) bus_dev;
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return pci->name;
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}
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/*
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* PCI bus operations table
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*
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*/
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struct bus_driver pci_driver __bus_driver = {
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.name = "PCI",
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.next_location = pci_next_location,
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.fill_device = pci_fill_device,
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.check_driver = pci_check_driver,
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.describe_device = pci_describe_device,
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.name_device = pci_name_device,
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};
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/*
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* Set device to be a busmaster in case BIOS neglected to do so. Also
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* adjust PCI latency timer to a reasonable value, 32.
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*/
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void adjust_pci_device ( struct pci_device *pci ) {
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unsigned short new_command, pci_command;
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unsigned char pci_latency;
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unsigned short new_command, pci_command;
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unsigned char pci_latency;
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pci_read_config_word ( pci, PCI_COMMAND, &pci_command );
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new_command = pci_command | PCI_COMMAND_MASTER | PCI_COMMAND_IO;
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if ( pci_command != new_command ) {
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DBG ( "PCI BIOS has not enabled device %hhx:%hhx.%d! "
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"Updating PCI command %hX->%hX\n",
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PCI_BUS ( pci->busdevfn ), PCI_DEV ( pci->busdevfn ),
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PCI_FUNC ( pci->busdevfn ), pci_command, new_command );
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DBG ( "PCI BIOS has not enabled device %02x:%02x.%x! "
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"Updating PCI command %04x->%04x\n", pci->bus,
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PCI_SLOT ( pci->devfn ), PCI_FUNC ( pci->devfn ),
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pci_command, new_command );
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pci_write_config_word ( pci, PCI_COMMAND, new_command );
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}
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pci_read_config_byte ( pci, PCI_LATENCY_TIMER, &pci_latency);
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if ( pci_latency < 32 ) {
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DBG ( "PCI device %hhx:%hhx.%d latency timer is "
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"unreasonably low at %d. Setting to 32.\n",
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PCI_BUS ( pci->busdevfn ), PCI_DEV ( pci->busdevfn ),
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PCI_FUNC ( pci->busdevfn ), pci_latency );
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DBG ( "PCI device %02x:%02x.%x latency timer is unreasonably "
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"low at %d. Setting to 32.\n", pci->bus,
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PCI_SLOT ( pci->devfn ), PCI_FUNC ( pci->devfn ),
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pci_latency );
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pci_write_config_byte ( pci, PCI_LATENCY_TIMER, 32);
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}
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}
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/*
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* Find the start of a pci resource.
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/**
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* Register PCI device
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*
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* @v pci PCI device
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* @ret rc Return status code
|
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*
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* Searches for a driver for the PCI device. If a driver is found,
|
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* its probe() routine is called, and the device is added to the
|
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* device hierarchy.
|
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*/
|
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unsigned long pci_bar_start ( struct pci_device *pci, unsigned int index ) {
|
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uint32_t lo, hi;
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unsigned long bar;
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static int register_pcidev ( struct pci_device *pci ) {
|
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struct pci_driver *driver;
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struct pci_device_id *id;
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unsigned int i;
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int rc;
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|
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pci_read_config_dword ( pci, index, &lo );
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if ( lo & PCI_BASE_ADDRESS_SPACE_IO ) {
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bar = lo & PCI_BASE_ADDRESS_IO_MASK;
|
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} else {
|
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bar = 0;
|
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if ( ( lo & PCI_BASE_ADDRESS_MEM_TYPE_MASK ) ==
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PCI_BASE_ADDRESS_MEM_TYPE_64) {
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pci_read_config_dword ( pci, index + 4, &hi );
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if ( hi ) {
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#if ULONG_MAX > 0xffffffff
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bar = hi;
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bar <<= 32;
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#else
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printf ( "Unhandled 64bit BAR %08x:%08x\n",
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hi, lo );
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return -1UL;
|
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#endif
|
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DBG ( "Registering PCI device %02x:%02x.%x (%04x:%04x mem %lx "
|
||||
"io %lx irq %d)\n", pci->bus, PCI_SLOT ( pci->devfn ),
|
||||
PCI_FUNC ( pci->devfn ), pci->vendor, pci->device,
|
||||
pci->membase, pci->ioaddr, pci->irq );
|
||||
|
||||
for ( driver = pci_drivers ; driver < pci_drivers_end ; driver++ ) {
|
||||
for ( i = 0 ; i < driver->id_count ; i++ ) {
|
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id = &driver->ids[i];
|
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if ( ( id->vendor != pci->vendor ) ||
|
||||
( id->device != pci->device ) )
|
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continue;
|
||||
pci->driver = driver;
|
||||
pci->name = id->name;
|
||||
DBG ( "...using driver %s\n", pci->name );
|
||||
if ( ( rc = driver->probe ( pci, id ) ) != 0 ) {
|
||||
DBG ( "......probe failed\n" );
|
||||
continue;
|
||||
}
|
||||
list_add ( &pci->dev.siblings,
|
||||
&pci->dev.parent->children );
|
||||
return 0;
|
||||
}
|
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bar |= lo & PCI_BASE_ADDRESS_MEM_MASK;
|
||||
}
|
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return bar + pci_bus_base ( pci );
|
||||
}
|
||||
|
||||
/*
|
||||
* Find the size of a pci resource.
|
||||
*/
|
||||
unsigned long pci_bar_size ( struct pci_device *pci, unsigned int bar ) {
|
||||
uint32_t start, size;
|
||||
|
||||
/* Save the original bar */
|
||||
pci_read_config_dword ( pci, bar, &start );
|
||||
/* Compute which bits can be set */
|
||||
pci_write_config_dword ( pci, bar, ~0 );
|
||||
pci_read_config_dword ( pci, bar, &size );
|
||||
/* Restore the original size */
|
||||
pci_write_config_dword ( pci, bar, start );
|
||||
/* Find the significant bits */
|
||||
if ( start & PCI_BASE_ADDRESS_SPACE_IO ) {
|
||||
size &= PCI_BASE_ADDRESS_IO_MASK;
|
||||
} else {
|
||||
size &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
}
|
||||
/* Find the lowest bit set */
|
||||
size = size & ~( size - 1 );
|
||||
return size;
|
||||
DBG ( "...no driver found\n" );
|
||||
return -ENOTTY;
|
||||
}
|
||||
|
||||
/**
|
||||
* pci_find_capability - query for devices' capabilities
|
||||
* @pci: PCI device to query
|
||||
* @cap: capability code
|
||||
* Unregister a PCI device
|
||||
*
|
||||
* Tell if a device supports a given PCI capability.
|
||||
* Returns the address of the requested capability structure within the
|
||||
* device's PCI configuration space or 0 in case the device does not
|
||||
* support it. Possible values for @cap:
|
||||
* @v pci PCI device
|
||||
*
|
||||
* %PCI_CAP_ID_PM Power Management
|
||||
*
|
||||
* %PCI_CAP_ID_AGP Accelerated Graphics Port
|
||||
*
|
||||
* %PCI_CAP_ID_VPD Vital Product Data
|
||||
*
|
||||
* %PCI_CAP_ID_SLOTID Slot Identification
|
||||
*
|
||||
* %PCI_CAP_ID_MSI Message Signalled Interrupts
|
||||
*
|
||||
* %PCI_CAP_ID_CHSWP CompactPCI HotSwap
|
||||
* Calls the device's driver's remove() routine, and removes the
|
||||
* device from the device hierarchy.
|
||||
*/
|
||||
int pci_find_capability ( struct pci_device *pci, int cap ) {
|
||||
uint16_t status;
|
||||
uint8_t pos, id;
|
||||
uint8_t hdr_type;
|
||||
int ttl = 48;
|
||||
static void unregister_pcidev ( struct pci_device *pci ) {
|
||||
pci->driver->remove ( pci );
|
||||
list_del ( &pci->dev.siblings );
|
||||
DBG ( "Unregistered PCI device %02x:%02x.%x\n", pci->bus,
|
||||
PCI_SLOT ( pci->devfn ), PCI_FUNC ( pci->devfn ) );
|
||||
}
|
||||
|
||||
pci_read_config_word ( pci, PCI_STATUS, &status );
|
||||
if ( ! ( status & PCI_STATUS_CAP_LIST ) )
|
||||
return 0;
|
||||
/**
|
||||
* Probe PCI root bus
|
||||
*
|
||||
* @v rootdev PCI bus root device
|
||||
*
|
||||
* Scans the PCI bus for devices and registers all devices it can
|
||||
* find.
|
||||
*/
|
||||
static int pcibus_probe ( struct root_device *rootdev ) {
|
||||
struct pci_device *pci = NULL;
|
||||
unsigned int bus;
|
||||
unsigned int devfn;
|
||||
uint8_t hdrtype;
|
||||
uint32_t tmp;
|
||||
int rc;
|
||||
|
||||
pci_read_config_byte ( pci, PCI_HEADER_TYPE, &hdr_type );
|
||||
switch ( hdr_type & 0x7F ) {
|
||||
case PCI_HEADER_TYPE_NORMAL:
|
||||
case PCI_HEADER_TYPE_BRIDGE:
|
||||
default:
|
||||
pci_read_config_byte ( pci, PCI_CAPABILITY_LIST, &pos );
|
||||
break;
|
||||
case PCI_HEADER_TYPE_CARDBUS:
|
||||
pci_read_config_byte ( pci, PCI_CB_CAPABILITY_LIST, &pos );
|
||||
break;
|
||||
}
|
||||
while ( ttl-- && pos >= 0x40 ) {
|
||||
pos &= ~3;
|
||||
pci_read_config_byte ( pci, pos + PCI_CAP_LIST_ID, &id );
|
||||
DBG ( "PCI Capability: %d\n", id );
|
||||
if ( id == 0xff )
|
||||
break;
|
||||
if ( id == cap )
|
||||
return pos;
|
||||
pci_read_config_byte ( pci, pos + PCI_CAP_LIST_NEXT, &pos );
|
||||
for ( bus = 0 ; bus <= pci_max_bus ; bus++ ) {
|
||||
for ( devfn = 0 ; devfn <= 0xff ; devfn++ ) {
|
||||
|
||||
/* Allocate struct pci_device */
|
||||
if ( ! pci )
|
||||
pci = malloc ( sizeof ( *pci ) );
|
||||
if ( ! pci ) {
|
||||
rc = -ENOMEM;
|
||||
goto err;
|
||||
}
|
||||
memset ( pci, 0, sizeof ( *pci ) );
|
||||
pci->bus = bus;
|
||||
pci->devfn = devfn;
|
||||
|
||||
/* Skip all but the first function on
|
||||
* non-multifunction cards
|
||||
*/
|
||||
if ( PCI_FUNC ( devfn ) == 0 ) {
|
||||
pci_read_config_byte ( pci, PCI_HEADER_TYPE,
|
||||
&hdrtype );
|
||||
} else if ( ! ( hdrtype & 0x80 ) ) {
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Check for physical device presence */
|
||||
pci_read_config_dword ( pci, PCI_VENDOR_ID, &tmp );
|
||||
if ( ( tmp == 0xffffffff ) || ( tmp == 0 ) )
|
||||
continue;
|
||||
|
||||
/* Populate struct pci_device */
|
||||
pci->vendor = ( tmp & 0xffff );
|
||||
pci->device = ( tmp >> 16 );
|
||||
pci_read_config_dword ( pci, PCI_REVISION, &tmp );
|
||||
pci->class = ( tmp >> 8 );
|
||||
pci_read_config_byte ( pci, PCI_INTERRUPT_LINE,
|
||||
&pci->irq );
|
||||
pci_read_bases ( pci );
|
||||
INIT_LIST_HEAD ( &pci->dev.children );
|
||||
pci->dev.parent = &rootdev->dev;
|
||||
|
||||
/* Look for a driver */
|
||||
if ( register_pcidev ( pci ) == 0 ) {
|
||||
/* pcidev registered, we can drop our ref */
|
||||
pci = NULL;
|
||||
} else {
|
||||
/* Not registered; re-use struct pci_device */
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
free ( pci );
|
||||
return 0;
|
||||
|
||||
err:
|
||||
free ( pci );
|
||||
pcibus_remove ( rootdev );
|
||||
return rc;
|
||||
}
|
||||
|
||||
/*
|
||||
* Fill in a nic structure
|
||||
/**
|
||||
* Remove PCI root bus
|
||||
*
|
||||
* @v rootdev PCI bus root device
|
||||
*/
|
||||
void pci_fill_nic ( struct nic *nic, struct pci_device *pci ) {
|
||||
static void pcibus_remove ( struct root_device *rootdev ) {
|
||||
struct pci_device *pci;
|
||||
struct pci_device *tmp;
|
||||
|
||||
/* Fill in ioaddr and irqno */
|
||||
nic->ioaddr = pci->ioaddr;
|
||||
nic->irqno = pci->irq;
|
||||
|
||||
/* Fill in DHCP device ID structure */
|
||||
nic->dhcp_dev_id.bus_type = PCI_BUS_TYPE;
|
||||
nic->dhcp_dev_id.vendor_id = htons ( pci->vendor_id );
|
||||
nic->dhcp_dev_id.device_id = htons ( pci->device_id );
|
||||
list_for_each_entry_safe ( pci, tmp, &rootdev->dev.children,
|
||||
dev.siblings ) {
|
||||
unregister_pcidev ( pci );
|
||||
free ( pci );
|
||||
}
|
||||
}
|
||||
|
||||
/** PCI bus root device driver */
|
||||
static struct root_driver pci_root_driver = {
|
||||
.probe = pcibus_probe,
|
||||
.remove = pcibus_remove,
|
||||
};
|
||||
|
||||
/** PCI bus root device */
|
||||
struct root_device pci_root_device __root_device = {
|
||||
.name = "PCI",
|
||||
.driver = &pci_root_driver,
|
||||
.dev = {
|
||||
.children = LIST_HEAD_INIT ( pci_root_device.dev.children ),
|
||||
},
|
||||
};
|
||||
|
||||
79
src/drivers/bus/pciextra.c
Normal file
79
src/drivers/bus/pciextra.c
Normal file
@@ -0,0 +1,79 @@
|
||||
#include <stdint.h>
|
||||
#include <gpxe/pci.h>
|
||||
|
||||
/**
|
||||
* Look for a PCI capability
|
||||
*
|
||||
* @v pci PCI device to query
|
||||
* @v cap Capability code
|
||||
* @ret address Address of capability, or 0 if not found
|
||||
*
|
||||
* Determine whether or not a device supports a given PCI capability.
|
||||
* Returns the address of the requested capability structure within
|
||||
* the device's PCI configuration space, or 0 if the device does not
|
||||
* support it.
|
||||
*/
|
||||
int pci_find_capability ( struct pci_device *pci, int cap ) {
|
||||
uint16_t status;
|
||||
uint8_t pos, id;
|
||||
uint8_t hdr_type;
|
||||
int ttl = 48;
|
||||
|
||||
pci_read_config_word ( pci, PCI_STATUS, &status );
|
||||
if ( ! ( status & PCI_STATUS_CAP_LIST ) )
|
||||
return 0;
|
||||
|
||||
pci_read_config_byte ( pci, PCI_HEADER_TYPE, &hdr_type );
|
||||
switch ( hdr_type & 0x7F ) {
|
||||
case PCI_HEADER_TYPE_NORMAL:
|
||||
case PCI_HEADER_TYPE_BRIDGE:
|
||||
default:
|
||||
pci_read_config_byte ( pci, PCI_CAPABILITY_LIST, &pos );
|
||||
break;
|
||||
case PCI_HEADER_TYPE_CARDBUS:
|
||||
pci_read_config_byte ( pci, PCI_CB_CAPABILITY_LIST, &pos );
|
||||
break;
|
||||
}
|
||||
while ( ttl-- && pos >= 0x40 ) {
|
||||
pos &= ~3;
|
||||
pci_read_config_byte ( pci, pos + PCI_CAP_LIST_ID, &id );
|
||||
DBG ( "PCI Capability: %d\n", id );
|
||||
if ( id == 0xff )
|
||||
break;
|
||||
if ( id == cap )
|
||||
return pos;
|
||||
pci_read_config_byte ( pci, pos + PCI_CAP_LIST_NEXT, &pos );
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Find the size of a PCI BAR
|
||||
*
|
||||
* @v pci PCI device
|
||||
* @v reg PCI register number
|
||||
* @ret size BAR size
|
||||
*
|
||||
* It should not be necessary for any Etherboot code to call this
|
||||
* function.
|
||||
*/
|
||||
unsigned long pci_bar_size ( struct pci_device *pci, unsigned int reg ) {
|
||||
uint32_t start, size;
|
||||
|
||||
/* Save the original bar */
|
||||
pci_read_config_dword ( pci, reg, &start );
|
||||
/* Compute which bits can be set */
|
||||
pci_write_config_dword ( pci, reg, ~0 );
|
||||
pci_read_config_dword ( pci, reg, &size );
|
||||
/* Restore the original size */
|
||||
pci_write_config_dword ( pci, reg, start );
|
||||
/* Find the significant bits */
|
||||
if ( start & PCI_BASE_ADDRESS_SPACE_IO ) {
|
||||
size &= PCI_BASE_ADDRESS_IO_MASK;
|
||||
} else {
|
||||
size &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
}
|
||||
/* Find the lowest bit set */
|
||||
size = size & ~( size - 1 );
|
||||
return size;
|
||||
}
|
||||
Reference in New Issue
Block a user