Restructured PCI subsystem to fit the new device model.

Generic PCI code now handles 64-bit BARs correctly when setting
"membase"; drivers should need to call pci_bar_start() only if they want
to use BARs other than the first memory or I/O BAR.

Split rarely-used PCI functions out into pciextra.c.

Core PCI code is now 662 bytes (down from 1308 bytes in Etherboot 5.4).
284 bytes of this saving comes from the pci/pciextra split.

Cosmetic changes to lots of drivers (e.g. vendor_id->vendor in order to
match the names used in Linux).

src/arch/i386/core/pci_io.c

@@ -21,8 +21,9 @@
 /* Macros for direct PCI access */
 #define CONFIG_ADDRESS	0xcf8
 #define CONFIG_DATA	0xcfc
-#define CONFIG_CMD( pci, where ) \
-	( 0x80000000 | (pci->busdevfn << 8) | (where & ~3) )
+#define CONFIG_CMD( pci, where )					\
+	( 0x80000000 | ( pci->bus << 16 ) | ( pci->devfn << 8 ) |	\
+	  ( where & ~3 ) )
 
 /* Signatures for PCI BIOS */
 #define BIOS_SIG(a,b,c,d)	( ( a<<0 ) + ( b<<8 ) + ( c<<16 ) + ( d<<24 ) )
@@ -343,8 +344,9 @@ INIT_FN ( INIT_PCIBIOS, find_pcibios32, NULL, NULL );
 			    "=S" ( discard_S ), "=D" ( discard_D )	\
 			  : "a" ( ( PCIBIOS_PCI_FUNCTION_ID << 8 )	\
 				  + command ),			       	\
-			    "b" ( pci->busdevfn ), "c" ( value ),	\
-			    "D" ( where ), "S" ( pcibios32_entry )	\
+			    "b" ( ( pci->bus << 8 ) | pci->devfn ),	\
+			    "c" ( value ), "D" ( where ),		\
+			    "S" ( pcibios32_entry )			\
 			  : "edx", "ebp" );				\
 									\
 		( ret >> 8 );						\