mirror of
https://github.com/ipxe/ipxe
synced 2025-12-19 19:49:45 +03:00
[x86_64] Fix assorted 64-bit compilation errors and warnings
Remove various 32-bit assumptions scattered throughout the codebase. The code is still not necessarily 64-bit clean, but will at least compile.
This commit is contained in:
@@ -133,14 +133,14 @@
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/* Structure/enum declaration ------------------------------- */
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struct tx_desc {
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u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
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u32 tx_buf_ptr; /* Data for us */
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u32 /* struct tx_desc * */ next_tx_desc;
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void * tx_buf_ptr; /* Data for us */
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struct tx_desc * next_tx_desc;
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} __attribute__ ((aligned(32)));
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struct rx_desc {
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u32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
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u32 rx_skb_ptr; /* Data for us */
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u32 /* struct rx_desc * */ next_rx_desc;
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void * rx_skb_ptr; /* Data for us */
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struct rx_desc * next_rx_desc;
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} __attribute__ ((aligned(32)));
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static struct dmfe_private {
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@@ -522,30 +522,30 @@ static void dmfe_descriptor_init(struct nic *nic __unused, unsigned long ioaddr)
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/* Init Transmit chain */
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for (i = 0; i < TX_DESC_CNT; i++) {
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txd[i].tx_buf_ptr = (u32) & txb[i];
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txd[i].tx_buf_ptr = &txb[i];
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txd[i].tdes0 = cpu_to_le32(0);
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txd[i].tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
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txd[i].tdes2 = cpu_to_le32(virt_to_bus(&txb[i]));
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txd[i].tdes3 = cpu_to_le32(virt_to_bus(&txd[i + 1]));
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txd[i].next_tx_desc = virt_to_le32desc(&txd[i + 1]);
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txd[i].next_tx_desc = &txd[i + 1];
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}
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/* Mark the last entry as wrapping the ring */
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txd[i - 1].tdes3 = virt_to_le32desc(&txd[0]);
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txd[i - 1].next_tx_desc = (u32) & txd[0];
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txd[i - 1].next_tx_desc = &txd[0];
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/* receive descriptor chain */
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for (i = 0; i < RX_DESC_CNT; i++) {
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rxd[i].rx_skb_ptr = (u32) & rxb[i * RX_ALLOC_SIZE];
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rxd[i].rx_skb_ptr = &rxb[i * RX_ALLOC_SIZE];
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rxd[i].rdes0 = cpu_to_le32(0x80000000);
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rxd[i].rdes1 = cpu_to_le32(0x01000600);
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rxd[i].rdes2 =
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cpu_to_le32(virt_to_bus(&rxb[i * RX_ALLOC_SIZE]));
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rxd[i].rdes3 = cpu_to_le32(virt_to_bus(&rxd[i + 1]));
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rxd[i].next_rx_desc = virt_to_le32desc(&rxd[i + 1]);
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rxd[i].next_rx_desc = &rxd[i + 1];
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}
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/* Mark the last entry as wrapping the ring */
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rxd[i - 1].rdes3 = cpu_to_le32(virt_to_bus(&rxd[0]));
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rxd[i - 1].next_rx_desc = virt_to_le32desc(&rxd[0]);
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rxd[i - 1].next_rx_desc = &rxd[0];
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}
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@@ -22,6 +22,7 @@
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#include <assert.h>
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#include <byteswap.h>
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#include <console.h>
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#include <gpxe/io.h>
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#include <gpxe/pci.h>
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#include <gpxe/malloc.h>
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#include <gpxe/ethernet.h>
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@@ -1449,7 +1450,7 @@ falcon_spi_rw ( struct spi_bus* bus, struct spi_device *device,
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return -EINVAL;
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}
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EFAB_TRACE ( "Executing spi command %d on device %d at %d for %d bytes\n",
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EFAB_TRACE ( "Executing spi command %d on device %d at %d for %zd bytes\n",
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command, device_id, address, len );
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/* The bus must be idle */
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@@ -1497,7 +1498,7 @@ falcon_spi_rw ( struct spi_bus* bus, struct spi_device *device,
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fail2:
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fail1:
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EFAB_ERR ( "Failed SPI command %d to device %d address 0x%x len 0x%x\n",
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EFAB_ERR ( "Failed SPI command %d to device %d address 0x%x len 0x%zx\n",
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command, device_id, address, len );
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return rc;
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@@ -3763,7 +3764,7 @@ efab_transmit ( struct net_device *netdev, struct io_buffer *iob )
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assert ( tx_queue->buf[buf_id] == NULL );
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tx_queue->buf[buf_id] = iob;
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EFAB_TRACE ( "tx_buf[%d] for iob %p data %p len %d\n",
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EFAB_TRACE ( "tx_buf[%d] for iob %p data %p len %zd\n",
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buf_id, iob, iob->data, iob_len ( iob ) );
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/* Form the descriptor, and push it to hardware */
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@@ -37,6 +37,7 @@
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#include <gpxe/umalloc.h>
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#include <byteswap.h>
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#include <unistd.h>
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#include <gpxe/io.h>
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#include <gpxe/pci.h>
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#include <gpxe/ethernet.h>
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#include <gpxe/netdevice.h>
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@@ -1618,8 +1619,8 @@ mtnic_disable(struct pci_device *pci)
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free(priv->cmd.buf);
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iounmap(priv->hcr);
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ufree((u32)priv->fw.fw_pages.buf);
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ufree((u32)priv->fw.extra_pages.buf);
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ufree((intptr_t)priv->fw.fw_pages.buf);
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ufree((intptr_t)priv->fw.extra_pages.buf);
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free(priv->eq.buf);
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iounmap(priv->eq_db);
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priv->state = CARD_DOWN;
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@@ -118,7 +118,7 @@ static const char hardcoded_ssid[] = "";
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typedef struct hfa384x
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{
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UINT32 iobase;
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UINT32 membase;
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void *membase;
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UINT16 lastcmd;
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UINT16 status; /* in host order */
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UINT16 resp0; /* in host order */
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@@ -22,14 +22,11 @@ $Id$
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static int prism2_pci_probe ( struct nic *nic, struct pci_device *pci ) {
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hfa384x_t *hw = &hw_global;
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uint32_t membase = 0; /* Prism2.5 Memory Base */
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pci_read_config_dword( pci, PRISM2_PCI_MEM_BASE, &membase);
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membase &= PCI_BASE_ADDRESS_MEM_MASK;
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hw->membase = (uint32_t) phys_to_virt(membase);
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printf ( "Prism2.5 has registers at %#lx\n", hw->membase );
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printf ( "Prism2.5 has registers at %#lx\n", pci->membase );
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hw->membase = ioremap ( pci->membase, 0x100 );
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nic->ioaddr = hw->membase;
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nic->ioaddr = pci->membase;
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nic->irqno = 0;
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return prism2_probe ( nic, hw );
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@@ -48,7 +48,6 @@ static int prism2_find_plx ( hfa384x_t *hw, struct pci_device *p )
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iobase &= PCI_BASE_ADDRESS_IO_MASK;
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/* Fill out hw structure */
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hw->membase = attr_mem;
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hw->iobase = iobase;
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printf ( "PLX9052 has local config registers at %#x\n", plx_lcr );
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printf ( "Prism2 has attribute memory at %#x and I/O base at %#x\n", attr_mem, iobase );
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@@ -1194,40 +1194,44 @@ rhine_reset (struct nic *nic)
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int ioaddr = tp->ioaddr;
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int i, j;
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int FDXFlag, CRbak;
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int rx_ring_tmp, rx_ring_tmp1;
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int tx_ring_tmp, tx_ring_tmp1;
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int rx_bufs_tmp, rx_bufs_tmp1;
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int tx_bufs_tmp, tx_bufs_tmp1;
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void *rx_ring_tmp;
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void *tx_ring_tmp;
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void *rx_bufs_tmp;
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void *tx_bufs_tmp;
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unsigned long rx_ring_tmp1;
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unsigned long tx_ring_tmp1;
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unsigned long rx_bufs_tmp1;
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unsigned long tx_bufs_tmp1;
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/* printf ("rhine_reset\n"); */
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/* Soft reset the chip. */
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/*outb(CmdReset, ioaddr + ChipCmd); */
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tx_bufs_tmp = (int) rhine_buffers.txbuf;
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tx_ring_tmp = (int) rhine_buffers.txdesc;
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rx_bufs_tmp = (int) rhine_buffers.rxbuf;
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rx_ring_tmp = (int) rhine_buffers.rxdesc;
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tx_bufs_tmp = rhine_buffers.txbuf;
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tx_ring_tmp = rhine_buffers.txdesc;
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rx_bufs_tmp = rhine_buffers.rxbuf;
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rx_ring_tmp = rhine_buffers.rxdesc;
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/* tune RD TD 32 byte alignment */
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rx_ring_tmp1 = (int) virt_to_bus ((char *) rx_ring_tmp);
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rx_ring_tmp1 = virt_to_bus ( rx_ring_tmp );
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j = (rx_ring_tmp1 + 32) & (~0x1f);
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/* printf ("txring[%d]", j); */
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tp->rx_ring = (struct rhine_rx_desc *) bus_to_virt (j);
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tx_ring_tmp1 = (int) virt_to_bus ((char *) tx_ring_tmp);
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tx_ring_tmp1 = virt_to_bus ( tx_ring_tmp );
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j = (tx_ring_tmp1 + 32) & (~0x1f);
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tp->tx_ring = (struct rhine_tx_desc *) bus_to_virt (j);
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/* printf ("rxring[%X]", j); */
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tx_bufs_tmp1 = (int) virt_to_bus ((char *) tx_bufs_tmp);
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tx_bufs_tmp1 = virt_to_bus ( tx_bufs_tmp );
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j = (int) (tx_bufs_tmp1 + 32) & (~0x1f);
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tx_bufs_tmp = (int) bus_to_virt (j);
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tx_bufs_tmp = bus_to_virt (j);
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/* printf ("txb[%X]", j); */
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rx_bufs_tmp1 = (int) virt_to_bus ((char *) rx_bufs_tmp);
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rx_bufs_tmp1 = virt_to_bus ( rx_bufs_tmp );
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j = (int) (rx_bufs_tmp1 + 32) & (~0x1f);
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rx_bufs_tmp = (int) bus_to_virt (j);
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rx_bufs_tmp = bus_to_virt (j);
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/* printf ("rxb[%X][%X]", rx_bufs_tmp1, j); */
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for (i = 0; i < RX_RING_SIZE; i++)
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@@ -550,7 +550,7 @@ static void velocity_transmit(struct nic *nic, const char *dest, /* Destination
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vptr->td_rings[entry].tdesc0.pktsize = pktlen;
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vptr->td_rings[entry].td_buf[0].pa_low = virt_to_bus(ptxb);
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vptr->td_rings[entry].td_buf[0].pa_high &=
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cpu_to_le32(0xffff0000L);
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cpu_to_le32(0xffff0000UL);
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vptr->td_rings[entry].td_buf[0].bufsize =
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vptr->td_rings[entry].tdesc0.pktsize;
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vptr->td_rings[entry].tdesc1.CMDZ = 2;
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