pseudo_bit_trgid_31_0[0x00020];/* Remote GID[31:0] if G bit is set. Must be set to 0x2 if G bit is cleared. */
/* -------------- */
};
/* Send doorbell */
structhermonprm_send_doorbell_st{/* Little Endian */
pseudo_bit_tnopcode[0x00005];/* Opcode of descriptor to be executed */
pseudo_bit_tf[0x00001];/* Fence bit. If set, descriptor is fenced */
pseudo_bit_treserved0[0x00002];
pseudo_bit_twqe_counter[0x00010];/* Modulo-64K counter of WQEs posted to the QP since its creation excluding the newly posted WQEs in this doorbell. Should be zero for the first doorbell on the QP */
pseudo_bit_twqe_cnt[0x00008];/* Number of WQEs posted with this doorbell. Must be grater then zero. */
/* -------------- */
pseudo_bit_tnds[0x00006];/* Next descriptor size (in 16-byte chunks) */
pseudo_bit_treserved1[0x00002];
pseudo_bit_tqpn[0x00018];/* QP number this doorbell is rung on */
/* -------------- */
};
/* Send wqe segment data inline */
structhermonprm_wqe_segment_data_inline_st{/* Little Endian */
pseudo_bit_tbyte_count[0x0000a];/* Not including padding for 16Byte chunks */
pseudo_bit_treserved0[0x00015];
pseudo_bit_talways1[0x00001];
/* -------------- */
pseudo_bit_tdata[0x00018];/* Data may be more this segment size - in 16Byte chunks */
pseudo_bit_treserved1[0x00008];
/* -------------- */
pseudo_bit_treserved2[0x00040];
/* -------------- */
};
/* Send wqe segment data ptr */
structhermonprm_wqe_segment_data_ptr_st{/* Little Endian */
pseudo_bit_tbyte_count[0x0001f];
pseudo_bit_talways0[0x00001];
/* -------------- */
pseudo_bit_tl_key[0x00020];
/* -------------- */
pseudo_bit_tlocal_address_h[0x00020];
/* -------------- */
pseudo_bit_tlocal_address_l[0x00020];
/* -------------- */
};
/* Send wqe segment rd */
structhermonprm_local_invalidate_segment_st{/* Little Endian */
pseudo_bit_treserved0[0x00040];
/* -------------- */
pseudo_bit_tmem_key[0x00018];
pseudo_bit_treserved1[0x00008];
/* -------------- */
pseudo_bit_treserved2[0x000a0];
/* -------------- */
};
/* Fast_Registration_Segment ####michal - doesn't match PRM (fields were added, see below) new table size in bytes - 0x30 */
structhermonprm_fast_registration_segment_st{/* Little Endian */
pseudo_bit_treserved0[0x0001b];
pseudo_bit_tlr[0x00001];/* If set - Local Read access will be enabled */
pseudo_bit_tlw[0x00001];/* If set - Local Write access will be enabled */
pseudo_bit_trr[0x00001];/* If set - Remote Read access will be enabled */
pseudo_bit_trw[0x00001];/* If set - Remote Write access will be enabled */
pseudo_bit_ta[0x00001];/* If set - Remote Atomic access will be enabled */
/* -------------- */
pseudo_bit_tpbl_ptr_63_32[0x00020];/* Physical address pointer [63:32] to the physical buffer list ### michal - this field is replaced with mem_key .32 */
/* -------------- */
pseudo_bit_tmem_key[0x00020];/* Memory Key on which the fast registration is executed on. ###michal-this field is replaced with pbl_ptr_63_32 */
/* -------------- */
pseudo_bit_tpage_size[0x00005];/* Page size used for the region. Actual size is [4K]*2^Page_size bytes.
pseudo_bit_tzb[0x00001];/* Zero Based Region ###michal - field doesn't exsist (see replacement above) */
pseudo_bit_tpbl_ptr_31_8[0x00018];/* Physical address pointer [31:8] to the physical buffer list ###michal - field doesn't exsist (see replacement above) */
/* -------------- */
pseudo_bit_tstart_address_h[0x00020];/* Start Address[63:32] - Virtual Address where this region starts */
/* -------------- */
pseudo_bit_tstart_address_l[0x00020];/* Start Address[31:0] - Virtual Address where this region starts */
/* -------------- */
pseudo_bit_treg_len_h[0x00020];/* Region Length[63:32] */
/* -------------- */
pseudo_bit_treg_len_l[0x00020];/* Region Length[31:0] */
/* -------------- */
};
/* Send wqe segment atomic */
structhermonprm_wqe_segment_atomic_st{/* Little Endian */
pseudo_bit_tswap_add_h[0x00020];
/* -------------- */
pseudo_bit_tswap_add_l[0x00020];
/* -------------- */
pseudo_bit_tcompare_h[0x00020];
/* -------------- */
pseudo_bit_tcompare_l[0x00020];
/* -------------- */
};
/* Send wqe segment remote address */
structhermonprm_wqe_segment_remote_address_st{/* Little Endian */
pseudo_bit_tremote_virt_addr_h[0x00020];
/* -------------- */
pseudo_bit_tremote_virt_addr_l[0x00020];
/* -------------- */
pseudo_bit_trkey[0x00020];
/* -------------- */
pseudo_bit_treserved0[0x00020];
/* -------------- */
};
/* end wqe segment bind */
structhermonprm_wqe_segment_bind_st{/* Little Endian */
pseudo_bit_treserved0[0x0001d];
pseudo_bit_trr[0x00001];/* If set, Remote Read Enable for bound window. */
pseudo_bit_trw[0x00001];/* If set, Remote Write Enable for bound window.
*/
pseudo_bit_ta[0x00001];/* If set, Atomic Enable for bound window. */
/* -------------- */
pseudo_bit_treserved1[0x0001e];
pseudo_bit_tzb[0x00001];/* If set, Window is Zero Based. */
pseudo_bit_ttype[0x00001];/* Window type.
0-Typeonewindow
1-Typetwowindow
*/
/* -------------- */
pseudo_bit_tnew_rkey[0x00020];/* The new RKey of window to bind */
/* -------------- */
pseudo_bit_tregion_lkey[0x00020];/* Local key of region, which window will be bound to */
/* -------------- */
pseudo_bit_tstart_address_h[0x00020];
/* -------------- */
pseudo_bit_tstart_address_l[0x00020];
/* -------------- */
pseudo_bit_tlength_h[0x00020];
/* -------------- */
pseudo_bit_tlength_l[0x00020];
/* -------------- */
};
/* Send wqe segment ud */
structhermonprm_wqe_segment_ud_st{/* Little Endian */
structhermonprm_ud_address_vector_stud_address_vector;/* UD Address Vector */
/* -------------- */
pseudo_bit_tdestination_qp[0x00018];
pseudo_bit_treserved0[0x00008];
/* -------------- */
pseudo_bit_tq_key[0x00020];
/* -------------- */
pseudo_bit_treserved1[0x00040];
/* -------------- */
};
/* Send wqe segment rd */
structhermonprm_wqe_segment_rd_st{/* Little Endian */
pseudo_bit_tdestination_qp[0x00018];
pseudo_bit_treserved0[0x00008];
/* -------------- */
pseudo_bit_tq_key[0x00020];
/* -------------- */
pseudo_bit_treserved1[0x00040];
/* -------------- */
};
/* Send wqe segment ctrl */
structhermonprm_wqe_segment_ctrl_send_st{/* Little Endian */
pseudo_bit_topcode[0x00005];
pseudo_bit_treserved0[0x0001a];
pseudo_bit_towner[0x00001];
/* -------------- */
pseudo_bit_tds[0x00006];/* descriptor (wqe) size in 16bytes chunk */
pseudo_bit_tc[0x00002];/* completion required: 0b00 - no 0b11 - yes */
pseudo_bit_tip[0x00001];/* When set, InfiniHost III Ex will calculate the IP checksum of the IP header that is present immediately after the IPoverIB encapsulation header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first IP header following the IPoverIB encapsulation header. Not Valid for IPv6 packets */
pseudo_bit_ttcp_udp[0x00001];/* When set, InfiniHost III Ex will calculate the TCP/UDP checksum of the packet that is present immediately after the IP header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first TCP header following the IP header. This bit may be set only if the entire TCP/UDP segment is present in one IB packet */
pseudo_bit_treserved2[0x00001];
pseudo_bit_tso[0x00001];/* Strong Ordering - when set, the WQE will be executed only after all previous WQEs have been executed. Can be set for RC WQEs only. This bit must be set in type two BIND, Fast Registration and Local invalidate operations. */
pseudo_bit_tsrc_remote_buf[0x00018];
/* -------------- */
pseudo_bit_timmediate[0x00020];/* If the OpCode encodes an operation with Immediate (RDMA-write/SEND), This field will hold the Immediate data to be sent. If the OpCode encodes send and invalidate operations, this field holds the Invalidation key to be inserted into the packet; otherwise, this field is reserved. */
/* -------------- */
};
/* Address Path # ###michal - match to PRM */
structhermonprm_address_path_st{/* Little Endian */
pseudo_bit_tpkey_index[0x00007];/* PKey table index */
pseudo_bit_treserved0[0x00016];
pseudo_bit_tsv[0x00001];/* Service VLAN on QP */
pseudo_bit_tcv[0x00001];/* Customer VLAN in QP */
pseudo_bit_tfl[0x00001];/* Force LoopBack */
/* -------------- */
pseudo_bit_trlid[0x00010];/* Remote (Destination) LID */
pseudo_bit_tmy_lid_smac_idx[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */
pseudo_bit_tgrh_ip[0x00001];/* Global address enable - if set, GRH will be formed for packet header */
pseudo_bit_treserved1[0x00008];
/* -------------- */
pseudo_bit_thop_limit[0x00008];/* IPv6 hop limit */
pseudo_bit_tmax_stat_rate[0x00004];/* Maximum static rate control.
0-100%injectionrate
1-25%injectionrate
2-12.5%injectionrate
3-50%injectionrate
7:2.5Gb/s.
8:10Gb/s.
9:30Gb/s.
10:5Gb/s.
11:20Gb/s.
12:40Gb/s.
13:60Gb/s.
14:80Gb/s.
15:120Gb/s.*/
pseudo_bit_treserved2[0x00004];
pseudo_bit_tmgid_index[0x00007];/* Index to port GID table */
pseudo_bit_treserved3[0x00004];
pseudo_bit_tack_timeout[0x00005];/* Local ACK timeout - Transport timer for activation of retransmission mechanism. Refer to IB spec Vol1 9.7.6.1.3 for further details.
pseudo_bit_tout_param_h[0x00020];/* Output Parameter: parameter[63:32] or pointer[63:32] to output mailbox (see command description) */
/* -------------- */
pseudo_bit_tout_param_l[0x00020];/* Output Parameter: parameter[31:0] or pointer[31:0] to output mailbox (see command description) */
/* -------------- */
pseudo_bit_treserved0[0x00010];
pseudo_bit_ttoken[0x00010];/* Software assigned token to the command, to uniquely identify it. The token is returned to the software in the EQE reported. */
/* -------------- */
pseudo_bit_topcode[0x0000c];/* Command opcode */
pseudo_bit_topcode_modifier[0x00004];/* Opcode Modifier, see specific description for each command. */
pseudo_bit_treserved1[0x00005];
pseudo_bit_tt[0x00001];/* Toggle */
pseudo_bit_te[0x00001];/* Event Request
0-Don'treportevent(softwarewillpolltheGObit)
1-ReporteventtoEQwhenthecommandcompletes*/
pseudo_bit_tgo[0x00001];/* Go (0=Software ownership for the HCR, 1=Hardware ownership for the HCR)
/* Multicast Group Member QP #### michal - match PRM */
structhermonprm_mgmqp_st{/* Little Endian */
pseudo_bit_tqpn_i[0x00018];/* QPN_i: QP number which is a member in this multicast group. Valid only if Qi bit is set. Length of the QPN_i list is set in INIT_HCA */
pseudo_bit_treserved0[0x00006];
pseudo_bit_tblck_lb[0x00001];/* Block self-loopback messages arriving to this qp */
pseudo_bit_tqi[0x00001];/* Qi: QPN_i is valid */
/* -------------- */
};
/* vsd */
structhermonprm_vsd_st{/* Little Endian */
pseudo_bit_tvsd_dw0[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw1[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw2[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw3[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw4[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw5[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw6[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw7[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw8[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw9[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw10[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw11[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw12[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw13[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw14[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw15[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw16[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw17[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw18[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw19[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw20[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw21[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw22[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw23[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw24[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw25[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw26[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw27[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw28[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw29[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw30[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw31[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw32[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw33[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw34[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw35[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw36[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw37[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw38[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw39[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw40[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw41[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw42[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw43[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw44[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw45[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw46[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw47[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw48[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw49[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw50[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw51[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw52[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw53[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw54[0x00020];
/* -------------- */
pseudo_bit_tvsd_dw55[0x00020];
/* -------------- */
};
/* UAR Parameters */
structhermonprm_uar_params_st{/* Little Endian */
pseudo_bit_treserved0[0x00040];
/* -------------- */
pseudo_bit_tuar_page_sz[0x00008];/* This field defines the size of each UAR page.
SizeofUARPageis4KB*2^UAR_Page_Size*/
pseudo_bit_tlog_max_uars[0x00004];/* Number of UARs supported is 2^log_max_UARs */
pseudo_bit_treserved1[0x00014];
/* -------------- */
pseudo_bit_treserved2[0x000a0];
/* -------------- */
};
/* Translation and Protection Tables Parameters */
structhermonprm_tptparams_st{/* Little Endian */
pseudo_bit_tdmpt_base_adr_h[0x00020];/* dMPT - Memory Protection Table base physical address [63:32].
pseudo_bit_tlog_mc_table_sz[0x00005];/* Log2 of the overall number of MC entries in the MCG table (includes both hash and auxiliary tables) */
pseudo_bit_treserved4[0x00013];
pseudo_bit_tmc_hash_fn[0x00003];/* Multicast hash function
0-Defaulthashfunction
other-reserved*/
pseudo_bit_treserved5[0x00005];
/* -------------- */
pseudo_bit_treserved6[0x00020];
/* -------------- */
};
/* QPC/EEC/CQC/EQC/RDB Parameters #### michal - doesn't match PRM (field name are differs. see below) */
structhermonprm_qpcbaseaddr_st{/* Little Endian */
pseudo_bit_treserved0[0x00080];
/* -------------- */
pseudo_bit_tqpc_base_addr_h[0x00020];/* QPC Base Address [63:32]
Tablemustbealignedonitssize*/
/* -------------- */
pseudo_bit_tlog_num_of_qp[0x00005];/* Log base 2 of number of supported QPs */
pseudo_bit_tqpc_base_addr_l[0x0001b];/* QPC Base Address [31:7]
Tablemustbealignedonitssize*/
/* -------------- */
pseudo_bit_treserved1[0x00040];
/* -------------- */
pseudo_bit_treserved2[0x00040];
/* -------------- */
pseudo_bit_tsrqc_base_addr_h[0x00020];/* SRQ Context Base Address [63:32]
Tablemustbealignedonitssize
Addressmaybesetto0xFFFFFFFFifSRQisnotsupported.*/
/* -------------- */
pseudo_bit_tlog_num_of_srq[0x00005];/* Log base 2 of number of supported SRQs. */
pseudo_bit_tsrqc_base_addr_l[0x0001b];/* SRQ Context Base Address [31:5]
Tablemustbealignedonitssize
Addressmaybesetto0xFFFFFFFFifSRQisnotsupported.*/
/* -------------- */
pseudo_bit_tcqc_base_addr_h[0x00020];/* CQC Base Address [63:32]
Tablemustbealignedonitssize*/
/* -------------- */
pseudo_bit_tlog_num_of_cq[0x00005];/* Log base 2 of number of supported CQs. */
pseudo_bit_tcqc_base_addr_l[0x0001b];/* CQC Base Address [31:6]
Tablemustbealignedonitssize*/
/* -------------- */
pseudo_bit_treserved3[0x00040];
/* -------------- */
pseudo_bit_taltc_base_addr_h[0x00020];/* AltC Base Address (altc_base_addr_h) [63:32]
TablehassamenumberofentriesasQPCtable.
Tablemustbealignedtoentrysize.*/
/* -------------- */
pseudo_bit_taltc_base_addr_l[0x00020];/* AltC Base Address (altc_base_addr_l) [31:0]
TablehassamenumberofentriesasQPCtable.
Tablemustbealignedtoentrysize.*/
/* -------------- */
pseudo_bit_treserved4[0x00040];
/* -------------- */
pseudo_bit_tauxc_base_addr_h[0x00020];
/* -------------- */
pseudo_bit_tauxc_base_addr_l[0x00020];
/* -------------- */
pseudo_bit_treserved5[0x00040];
/* -------------- */
pseudo_bit_teqc_base_addr_h[0x00020];/* EQC Base Address [63:32]
Addressmaybesetto0xFFFFFFFFifEQsarenotsupported.
Tablemustbealignedtoentrysize.*/
/* -------------- */
pseudo_bit_tlog_num_of_eq[0x00005];/* Log base 2 of number of supported EQs.
Mustbe6orlessinInfiniHost-III-EX.*/
pseudo_bit_teqc_base_addr_l[0x0001b];/* EQC Base Address [31:6]
Addressmaybesetto0xFFFFFFFFifEQsarenotsupported.
Tablemustbealignedtoentrysize.*/
/* -------------- */
pseudo_bit_treserved6[0x00040];
/* -------------- */
pseudo_bit_trdmardc_base_addr_h[0x00020];/* rdmardc_base_addr_h: Base address of table that holds remote read and remote atomic requests [63:32]. */
/* -------------- */
pseudo_bit_tlog_num_rd[0x00003];/* Log (base 2) of the maximum number of RdmaRdC entries per QP. This denotes the maximum number of outstanding reads/atomics as a responder. */
pseudo_bit_treserved7[0x00002];
pseudo_bit_trdmardc_base_addr_l[0x0001b];/* rdmardc_base_addr_l: Base address of table that holds remote read and remote atomic requests [31:0].
TablemustbealignedtoRDBentrysize(32bytes).*/
/* -------------- */
pseudo_bit_treserved8[0x00040];
/* -------------- */
};
/* Header_Log_Register */
structhermonprm_header_log_register_st{/* Little Endian */
pseudo_bit_tplace_holder[0x00020];
/* -------------- */
pseudo_bit_treserved0[0x00060];
/* -------------- */
};
/* Performance Monitors */
structhermonprm_performance_monitors_st{/* Little Endian */
pseudo_bit_te0[0x00001];/* Enables counting of respective performance counter */
pseudo_bit_te1[0x00001];/* Enables counting of respective performance counter */
pseudo_bit_te2[0x00001];/* Enables counting of respective performance counter */
pseudo_bit_treserved0[0x00001];
pseudo_bit_tr0[0x00001];/* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */
pseudo_bit_tr1[0x00001];/* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */
pseudo_bit_tr2[0x00001];/* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */
pseudo_bit_tf0[0x00001];/* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */
pseudo_bit_tf1[0x00001];/* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */
pseudo_bit_tf2[0x00001];/* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */
pseudo_bit_treserved3[0x00001];
pseudo_bit_tev_cnt1[0x00005];/* Specifies event to be counted by Event_counter1 See XXX for events' definition. */
pseudo_bit_treserved4[0x00003];
pseudo_bit_tev_cnt2[0x00005];/* Specifies event to be counted by Event_counter2 See XXX for events' definition. */
pseudo_bit_treserved5[0x00003];
/* -------------- */
pseudo_bit_tclock_counter[0x00020];
/* -------------- */
pseudo_bit_tevent_counter1[0x00020];
/* -------------- */
pseudo_bit_tevent_counter2[0x00020];/* Read/write event counter, counting events specified by EvCntl and EvCnt2 fields repsectively. When the event counter reaches is maximum value of 0xFFFFFF, the next event will cause it to roll over to zero, set F1 or F2 bit respectively and generate interrupt by I1 I2 bit respectively. */
/* -------------- */
};
/* MLX WQE segment format */
structhermonprm_wqe_segment_ctrl_mlx_st{/* Little Endian */
pseudo_bit_topcode[0x00005];/* must be 0xA = SEND */
pseudo_bit_tfre[0x00001];/* Fast Registration Work Request Enabled. (Reserved for EE) */
pseudo_bit_treserved16[0x00001];
pseudo_bit_trnr_retry[0x00003];
pseudo_bit_tretry_count[0x00003];/* Transport timeout Retry count */
pseudo_bit_treserved17[0x00002];
pseudo_bit_tsra_max[0x00003];/* Maximum number of outstanding RDMA-read/Atomic operations allowed in the send queue. Maximum number is 2^SRA_Max. Must be zero in EE context. */
pseudo_bit_treserved18[0x00004];
pseudo_bit_tack_req_freq[0x00004];/* ACK required frequency. ACK required bit will be set in every 2^AckReqFreq packets at least. Not valid for RD QP. */
/* -------------- */
pseudo_bit_treserved19[0x00020];
/* -------------- */
pseudo_bit_tnext_send_psn[0x00018];/* Next PSN to be sent */
pseudo_bit_treserved20[0x00008];
/* -------------- */
pseudo_bit_tcqn_snd[0x00018];/* CQ number completions from the send queue to be reported to. Not valid (reserved) in EE context. */
pseudo_bit_treserved21[0x00008];
/* -------------- */
pseudo_bit_treserved22[0x00040];
/* -------------- */
pseudo_bit_tlast_acked_psn[0x00018];/* The last acknowledged PSN for the requester (QUERY_QPEE only) */
pseudo_bit_treserved23[0x00008];
/* -------------- */
pseudo_bit_tssn[0x00018];/* Requester Send Sequence Number (QUERY_QPEE only) */
pseudo_bit_tsrq[0x00001];/* SRQ - Shared Receive Queue. If this bit is set, then the QP is associated with a SRQ. Not valid (reserved) in EE context. */
pseudo_bit_treserved34[0x00007];
/* -------------- */
pseudo_bit_trmsn[0x00018];/* Responder current message sequence number (QUERY_QPEE only) */
pseudo_bit_treserved35[0x00008];
/* -------------- */
pseudo_bit_tsq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the SQ.
Mustbe0x0inSQinitialization.
(QUERY_QPEEonly).*/
pseudo_bit_trq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the RQ.
Mustbe0x0inRQinitialization.
(QUERY_QPEEonly).*/
/* -------------- */
pseudo_bit_treserved36[0x00040];
/* -------------- */
pseudo_bit_trmc_parent_qpn[0x00018];/* reliable multicast parent queue number */
pseudo_bit_ths[0x00001];/* Header Separation. If set, the byte count of the first scatter entry will be ignored. The buffer specified by the first scatter entry will contain packet headers (up to TCP). CQE will report number of bytes scattered to the first scatter entry. Intended for use on IPoverIB on UD QP or Raw Ethernet QP. */
pseudo_bit_tis[0x00001];/* when set - inline scatter is enabled for this RQ */
pseudo_bit_tmkey_rmp[0x00001];/* If set, MKey used to access TPT for incoming RDMA-write request is calculated by adding MKey from the packet to base_MKey field in the QPC. Can be set only for QPs that are not target for RDMA-read request. */
/* -------------- */
pseudo_bit_tbase_mkey[0x00018];/* Base Mkey bits [31:8]. Lower 8 bits must be zero. */
pseudo_bit_tnum_rmc_peers[0x00008];/* Number of remote peers in Reliable Multicast group */
/* -------------- */
pseudo_bit_tmtt_base_addr_h[0x00008];/* MTT Base Address [39:32] in ICM relative to INIT_HCA.mtt_base_addr */
pseudo_bit_treserved39[0x00010];
pseudo_bit_tlog2_page_size[0x00006];/* Log (base 2) of MTT page size in units of 4KByte */
pseudo_bit_treserved40[0x00002];
/* -------------- */
pseudo_bit_treserved41[0x00003];
pseudo_bit_tmtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] in ICM relative to INIT_HCA.mtt_base_addr */
/* -------------- */
pseudo_bit_tvft_lan[0x0000c];
pseudo_bit_tvft_prio[0x00003];/* The Priority filed in the VFT header for FCP */
pseudo_bit_treserved42[0x00001];
pseudo_bit_tcs_ctl[0x00009];/* The Priority filed in the VFT header for FCP */
pseudo_bit_treserved43[0x00006];
pseudo_bit_tve[0x00001];/* Should we add/check the VFT header */
/* -------------- */
pseudo_bit_texch_base[0x00010];/* For init QP only - The base exchanges */
pseudo_bit_treserved44[0x00008];
pseudo_bit_texch_size[0x00004];/* For CMMD QP only - The size (from base) exchanges is 2exchanges_size */
pseudo_bit_treserved45[0x00003];
pseudo_bit_tfc[0x00001];/* When set it mean that this QP is used for FIBRE CHANNEL. */
/* -------------- */
pseudo_bit_tremote_id[0x00018];/* Peer NX port ID */
pseudo_bit_treserved46[0x00008];
/* -------------- */
pseudo_bit_tfcp_mtu[0x0000a];/* In 4*Bytes units. The MTU Size */
pseudo_bit_treserved47[0x00006];
pseudo_bit_tmy_id_indx[0x00008];/* Index to My NX port ID table */
pseudo_bit_tvft_hop_count[0x00008];/* HopCnt value for the VFT header */
/* -------------- */
pseudo_bit_treserved48[0x000c0];
/* -------------- */
};
/* */
structhermonprm_mcg_qp_dw_st{/* Little Endian */
pseudo_bit_tqpn[0x00018];
pseudo_bit_treserved0[0x00006];
pseudo_bit_tblck_lb[0x00001];
pseudo_bit_treserved1[0x00001];
/* -------------- */
};
/* Clear Interrupt [63:0] #### michal - match to PRM */
structhermonprm_srq_context_st{/* Little Endian */
pseudo_bit_tsrqn[0x00018];/* SRQ number */
pseudo_bit_tlog_srq_size[0x00004];/* Log2 of the Number of WQEs in the Receive Queue.
Maximumvalueis0x10,i.e.16MWQEs.*/
pseudo_bit_tstate[0x00004];/* SRQ State:
1111-SWOwnership
0000-HWOwnership
0001-Error
ValidonlyonQUERY_SRQandHW2SW_SRQcommands.*/
/* -------------- */
pseudo_bit_tsrc_domain[0x00010];/* The Scalable RC Domain. Messages coming to receive ports specifying this SRQ as receive queue will be served only if SRC_Domain of the SRQ matches SRC_Domain of the transport QP of this message. */
pseudo_bit_treserved0[0x00008];
pseudo_bit_tlog_srq_stride[0x00003];/* Stride (max WQE size) on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes. */
pseudo_bit_treserved1[0x00005];
/* -------------- */
pseudo_bit_tcqn[0x00018];/* Completion Queue to report SRC messages directed to this SRQ. */
pseudo_bit_tpage_offset[0x00006];/* The offset of the first WQE from the beginning of 4Kbyte page (Figure 52,<2C>Work Queue Buffer Structure<72>) */
pseudo_bit_treserved2[0x00002];
/* -------------- */
pseudo_bit_treserved3[0x00020];
/* -------------- */
pseudo_bit_tmtt_base_addr_h[0x00008];/* MTT Base Address [39:32] in ICM relative to INIT_HCA.mtt_base_addr */
pseudo_bit_treserved4[0x00010];
pseudo_bit_tlog2_page_size[0x00006];/* Log (base 2) of MTT page size in units of 4KByte */
pseudo_bit_treserved5[0x00002];
/* -------------- */
pseudo_bit_treserved6[0x00003];
pseudo_bit_tmtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] in ICM relative to INIT_HCA.mtt_base_addr */
pseudo_bit_twqe_cnt[0x00010];/* WQE count on the SRQ. Valid only upon QUERY_SRQ and HW2SW_SRQ commands. */
pseudo_bit_tlwm[0x00010];/* Limit Water Mark - if the LWM is not zero, and the wqe_cnt drops below LWM when a WQE is dequeued from the SRQ, then an SRQ limit event is fired and the LWM is set to zero. Valid only upon QUERY_SRQ and HW2SW_SRQ commands. */
/* -------------- */
pseudo_bit_tsrq_wqe_counter[0x00010];/* A 16-bit counter incremented for each WQE posted to the SRQ. Must be 0x0 in SRQ initialization. Valid only upon the QUERY_SRQ command. */
pseudo_bit_treserved8[0x00010];
/* -------------- */
pseudo_bit_treserved9[0x00020];
/* -------------- */
pseudo_bit_tdb_record_addr_h[0x00020];/* SRQ DB Record physical address [63:32] */
/* -------------- */
pseudo_bit_treserved10[0x00002];
pseudo_bit_tdb_record_addr_l[0x0001e];/* SRQ DB Record physical address [31:2] */
/* -------------- */
};
/* PBL */
structhermonprm_pbl_st{/* Little Endian */
pseudo_bit_tmtt_0_h[0x00020];/* First MTT[63:32] */
/* -------------- */
pseudo_bit_tmtt_0_l[0x00020];/* First MTT[31:0] */
/* -------------- */
pseudo_bit_tmtt_1_h[0x00020];/* Second MTT[63:32] */
/* -------------- */
pseudo_bit_tmtt_1_l[0x00020];/* Second MTT[31:0] */
/* -------------- */
pseudo_bit_tmtt_2_h[0x00020];/* Third MTT[63:32] */
/* -------------- */
pseudo_bit_tmtt_2_l[0x00020];/* Third MTT[31:0] */
pseudo_bit_towner[0x00001];/* HW Flips this bit for every CQ warp around. Initialized to Zero. */
pseudo_bit_treserved3[0x00018];
/* -------------- */
};
/* Resize CQ Input Mailbox */
structhermonprm_resize_cq_st{/* Little Endian */
pseudo_bit_treserved0[0x00040];
/* -------------- */
pseudo_bit_treserved1[0x00006];
pseudo_bit_tpage_offset[0x00006];
pseudo_bit_treserved2[0x00014];
/* -------------- */
pseudo_bit_treserved3[0x00018];
pseudo_bit_tlog_cq_size[0x00005];/* Log (base 2) of the CQ size (in entries) */
pseudo_bit_treserved4[0x00003];
/* -------------- */
pseudo_bit_treserved5[0x00020];
/* -------------- */
pseudo_bit_tmtt_base_addr_h[0x00008];
pseudo_bit_treserved6[0x00010];
pseudo_bit_tlog2_page_size[0x00006];
pseudo_bit_treserved7[0x00002];
/* -------------- */
pseudo_bit_treserved8[0x00003];
pseudo_bit_tmtt_base_addr_l[0x0001d];
/* -------------- */
pseudo_bit_treserved9[0x00020];
/* -------------- */
pseudo_bit_treserved10[0x00100];
/* -------------- */
};
/* MAD_IFC Input Modifier */
structhermonprm_mad_ifc_input_modifier_st{/* Little Endian */
pseudo_bit_tport_number[0x00008];/* The packet reception port number (1 or 2). */
pseudo_bit_tmad_extended_info[0x00001];/* Mad_Extended_Info valid bit (MAD_IFC Input Mailbox data from offset 00100h and down). MAD_Extended_Info is read only if this bit is set.
/* Query Debug Message #### michal - gdror fixed */
structhermonprm_query_debug_msg_st{/* Little Endian */
pseudo_bit_tphy_addr_h[0x00020];/* Translation of the address in firmware area. High 32 bits. */
/* -------------- */
pseudo_bit_tv[0x00001];/* Physical translation is valid */
pseudo_bit_treserved0[0x0000b];
pseudo_bit_tphy_addr_l[0x00014];/* Translation of the address in firmware area. Low 32 bits. */
/* -------------- */
pseudo_bit_tfw_area_base[0x00020];/* Firmware area base address. The format strings and the trace buffers may be located starting from this address. */
/* -------------- */
pseudo_bit_tfw_area_size[0x00020];/* Firmware area size */
/* -------------- */
pseudo_bit_ttrc_hdr_sz[0x00020];/* Trace message header size in dwords. */
/* -------------- */
pseudo_bit_ttrc_arg_num[0x00020];/* The number of arguments per trace message. */
structhermonprm_receive_doorbell_st{/* Little Endian */
pseudo_bit_treserved0[0x00008];
pseudo_bit_twqe_counter[0x00010];/* Modulo-64K counter of WQEs posted on this queue since its creation. Should be zero for the first doorbell on the QP */
pseudo_bit_treserved1[0x00008];
/* -------------- */
pseudo_bit_treserved2[0x00005];
pseudo_bit_tsrq[0x00001];/* If set, this is a Shared Receive Queue */
pseudo_bit_treserved3[0x00002];
pseudo_bit_tqpn[0x00018];/* QP number or SRQ number this doorbell is rung on */
pseudo_bit_tlog_max_ra_res_qp[0x00006];/* Log2 of the Maximum number of outstanding RDMA read/Atomic per QP as a responder */
pseudo_bit_treserved16[0x0000a];
pseudo_bit_tlog_max_ra_req_qp[0x00006];/* Log2 of the maximum number of outstanding RDMA read/Atomic per QP as a requester */
pseudo_bit_treserved17[0x0000a];
/* -------------- */
pseudo_bit_tlog_max_ra_res_global[0x00006];/* Log2 of the maximum number of RDMA read/atomic operations the HCA responder can support globally. That implies the RDB table size. */
pseudo_bit_treserved18[0x0001a];
/* -------------- */
pseudo_bit_trsz_srq[0x00001];/* Ability to modify the maximum number of WRs per SRQ. */
pseudo_bit_treserved19[0x0001f];
/* -------------- */
pseudo_bit_tnum_ports[0x00004];/* Number of IB ports. */
pseudo_bit_tmax_vl_ib[0x00004];/* Maximum VLs supported on each port, excluding VL15 */
pseudo_bit_tib_port_width[0x00004];/* IB Port Width
1-1x
3-1x,4x
11-1x,4xor12x
else-Reserved*/
pseudo_bit_tib_mtu[0x00004];/* Maximum MTU Supported
0x0-Reserved
0x1-256
0x2-512
0x3-1024
0x4-2048
0x5-4096
0x6-0xFReserved*/
pseudo_bit_tlocal_ca_ack_delay[0x00005];/* The Local CA ACK Delay. This is the value recommended to be returned in Query HCA verb.
pseudo_bit_tlog_max_bf_pages[0x00006];/* Maximum number of BlueFlame pages is 2^log_max_bf_pages */
pseudo_bit_treserved32[0x00002];
pseudo_bit_tlog_max_bf_regs_per_page[0x00006];/* Maximum number of BlueFlame registers per page is 2^log_max_bf_regs_per_page. It may be that only the beginning of a page contains BlueFlame registers. */
pseudo_bit_treserved33[0x00002];
pseudo_bit_tlog_bf_reg_size[0x00005];/* BlueFlame register size in bytes is 2^log_bf_reg_size */
pseudo_bit_treserved34[0x0000a];
pseudo_bit_tbf[0x00001];/* If set to "1" then BlueFlame may be used. */
/* -------------- */
pseudo_bit_tmax_desc_sz_sq[0x00010];/* Max descriptor size in bytes for the send queue */
pseudo_bit_tmax_sg_sq[0x00008];/* The maximum S/G list elements in a SQ WQE (max_desc_sz/16 - 3) */
pseudo_bit_treserved35[0x00008];
/* -------------- */
pseudo_bit_tmax_desc_sz_rq[0x00010];/* Max descriptor size in bytes for the receive queue */
pseudo_bit_tmax_sg_rq[0x00008];/* The maximum S/G list elements in a RQ WQE (max_desc_sz/16 - 3) */
pseudo_bit_treserved36[0x00008];
/* -------------- */
pseudo_bit_treserved37[0x00001];
pseudo_bit_tfexch_base_mpt_31_25[0x00007];/* Hermon New. FC mpt base mpt number */
pseudo_bit_tfcp_ud_base_23_8[0x00010];/* Hermon New. FC ud QP base QPN */
pseudo_bit_tfexch_base_qp_23_16[0x00008];/* Hermon New. FC Exchange QP base QPN */
/* -------------- */
pseudo_bit_treserved38[0x00020];
/* -------------- */
pseudo_bit_tlog_max_mcg[0x00008];/* Log2 of the maximum number of multicast groups */
pseudo_bit_tnum_rsvd_mcgs[0x00004];/* The number of MGMs reserved for firmware use in the MGHT.
pseudo_bit_tmtt_entry_sz[0x00010];/* MTT entry size in Bytes for the device.
FortheInfiniHost-III-EXMT25208entrysizeis8bytes*/
/* -------------- */
pseudo_bit_tbmme[0x00001];/* Base Memory Management Extension Support */
pseudo_bit_twin_type[0x00001];/* Bound Type 2 Memory Window Association mechanism:
0-Type2A-QPNumberAssociation;or
1-Type2B-QPNumberandPDAssociation.*/
pseudo_bit_tmps[0x00001];/* Ability of this HCA to support multiple page sizes per Memory Region. */
pseudo_bit_tbl[0x00001];/* Ability of this HCA to support Block List Physical Buffer Lists. */
pseudo_bit_tzb[0x00001];/* Zero Based region/windows supported */
pseudo_bit_tlif[0x00001];/* Ability of this HCA to support Local Invalidate Fencing. */
pseudo_bit_treserved44[0x0001a];
/* -------------- */
pseudo_bit_tresd_lkey[0x00020];/* The value of the reserved Lkey for Base Memory Management Extension */
/* -------------- */
pseudo_bit_treserved45[0x00020];
/* -------------- */
pseudo_bit_tmax_icm_size_h[0x00020];/* Bits [63:32] of maximum ICM size InfiniHost III Ex support in bytes. */
/* -------------- */
pseudo_bit_tmax_icm_size_l[0x00020];/* Bits [31:0] of maximum ICM size InfiniHost III Ex support in bytes. */
/* -------------- */
pseudo_bit_treserved46[0x002c0];
/* -------------- */
};
/* QUERY_ADAPTER Parameters Block #### michal - gdror fixed */
structhermonprm_query_adapter_st{/* Little Endian */
pseudo_bit_treserved0[0x00080];
/* -------------- */
pseudo_bit_treserved1[0x00018];
pseudo_bit_tintapin[0x00008];/* Driver should set this field to INTR value in the event queue in order to get Express interrupt messages. */
/* -------------- */
pseudo_bit_treserved2[0x00060];
/* -------------- */
structhermonprm_vsd_stvsd;/* ###michal- this field was replaced by 2 fields : vsd .1664; vsd(continued/psid .128; */
/* -------------- */
};
/* QUERY_FW Parameters Block #### michal - doesn't match PRM */
structhermonprm_query_fw_st{/* Little Endian */
pseudo_bit_tfw_rev_major[0x00010];/* Firmware Revision - Major */
pseudo_bit_tfw_pages[0x00010];/* Amount of physical memory to be allocated for FW usage is in 4KByte pages. */
/* -------------- */
pseudo_bit_tfw_rev_minor[0x00010];/* Firmware Revision - Minor */
pseudo_bit_tfw_rev_subminor[0x00010];/* Firmware Sub-minor version (Patch level). */
/* -------------- */
pseudo_bit_tcmd_interface_rev[0x00010];/* Command Interface Interpreter Revision ID */
pseudo_bit_treserved0[0x00010];
/* -------------- */
pseudo_bit_tlog_max_outstanding_cmd[0x00008];/* Log2 of the maximum number of commands the HCR can support simultaneously */
pseudo_bit_treserved1[0x00017];
pseudo_bit_tdt[0x00001];/* Debug Trace Support
0-Debugtraceisnotsupported
1-Debugtraceissupported*/
/* -------------- */
pseudo_bit_treserved2[0x00001];
pseudo_bit_tccq[0x00001];/* CCQ support */
pseudo_bit_treserved3[0x00006];
pseudo_bit_tfw_seconds[0x00008];/* FW timestamp - seconds. Dispalyed as Hexadecimal number */
pseudo_bit_tfw_minutes[0x00008];/* FW timestamp - minutes. Dispalyed as Hexadecimal number */
pseudo_bit_tfw_hour[0x00008];/* FW timestamp - hour. Dispalyed as Hexadecimal number */
/* -------------- */
pseudo_bit_tfw_day[0x00008];/* FW timestamp - day. Dispalyed as Hexadecimal number */
pseudo_bit_tfw_month[0x00008];/* FW timestamp - month. Dispalyed as Hexadecimal number */
pseudo_bit_tfw_year[0x00010];/* FW timestamp - year. Dispalyed as Hexadecimal number (e.g. 0x2005) */
/* -------------- */
pseudo_bit_treserved4[0x00040];
/* -------------- */
pseudo_bit_tclr_int_base_offset_h[0x00020];/* Bits [63:32] of the Clear Interrupt registers offset from clr_int_bar register in PCIaddress space. Points to a 64-bit register. */
/* -------------- */
pseudo_bit_tclr_int_base_offset_l[0x00020];/* Bits [31:0] of the Clear Interrupt registers offset from clr_int_bar register in PCIaddress space. Points to a 64-bit register. */
/* -------------- */
pseudo_bit_treserved5[0x0001e];
pseudo_bit_tclr_int_bar[0x00002];/* PCI base address register (BAR) where clr_int register is located.
00-BAR0-1
01-BAR2-3
10-BAR4-5
11-Reserved
ThePCIBARsofConnectXare64bitBARs.
InConnectX,clr_intregisterislocatedonBAR0-1.*/
/* -------------- */
pseudo_bit_treserved6[0x00020];
/* -------------- */
pseudo_bit_terror_buf_offset_h[0x00020];/* Read Only buffer for catastrophic error reports (bits [63:32] of offset from error_buf_bar register in PCI address space.) */
/* -------------- */
pseudo_bit_terror_buf_offset_l[0x00020];/* Read Only buffer for catastrophic error reports (bits [31:0] of offset from error_buf_bar register in PCI address space.) */
/* -------------- */
pseudo_bit_terror_buf_size[0x00020];/* Size in words */
/* -------------- */
pseudo_bit_treserved7[0x0001e];
pseudo_bit_terror_buf_bar[0x00002];/* PCI base address register (BAR) where error_buf register is located.
00-BAR0-1
01-BAR2-3
10-BAR4-5
11-Reserved
ThePCIBARsofConnectXare64bitBARs.
InConnectX,error_bufregisterislocatedonBAR0-1.*/
/* -------------- */
pseudo_bit_treserved8[0x00600];
/* -------------- */
};
/* Memory Access Parameters for UD Address Vector Table */
structhermonprm_udavtable_memory_parameters_st{/* Little Endian */
pseudo_bit_tl_key[0x00020];/* L_Key used to access TPT */
/* -------------- */
pseudo_bit_tpd[0x00018];/* PD used by TPT for matching against PD of region entry being accessed. */
pseudo_bit_treserved0[0x00005];
pseudo_bit_txlation_en[0x00001];/* When cleared, address is physical address and no translation will be done. When set, address is virtual. */
pseudo_bit_treserved1[0x00002];
/* -------------- */
};
/* INIT_HCA & QUERY_HCA Parameters Block ####michal-doesn't match PRM (see differs below) new size in bytes:0x300 */
structhermonprm_init_hca_st{/* Little Endian */
pseudo_bit_treserved0[0x00018];
pseudo_bit_tversion[0x00008];
/* -------------- */
pseudo_bit_treserved1[0x00040];
/* -------------- */
pseudo_bit_treserved2[0x00010];
pseudo_bit_thca_core_clock[0x00010];/* Internal Clock freq in MHz */
/* -------------- */
pseudo_bit_trouter_qp[0x00018];/* QP number for router mode (8 LSBits should be 0). Low order 8 bits are taken from the TClass field of the incoming packet.
ValidonlyifREbitisset*/
pseudo_bit_treserved3[0x00005];
pseudo_bit_tipr2[0x00001];/* Hermon New. IP router on port 2 */
pseudo_bit_tipr1[0x00001];/* Hermon New. IP router on port 1 */
pseudo_bit_the[0x00001];/* Host Endianess - Used for Atomic Operations
0-HostisLittleEndian
1-HostisBigendian
*/
pseudo_bit_treserved4[0x00001];
pseudo_bit_tce[0x00001];/* Checksum Enabled - when Set IPoverIB checksum generation & checking is enabled */
pseudo_bit_treserved5[0x0001c];
/* -------------- */
pseudo_bit_treserved6[0x00040];
/* -------------- */
structhermonprm_qpcbaseaddr_stqpc_eec_cqc_eqc_rdb_parameters;/* ## michal - this field has chenged to - "qpc_cqc_eqc_parameters" - gdror, this is ok for now */
/* -------------- */
pseudo_bit_treserved7[0x00100];
/* -------------- */
structhermonprm_multicastparam_stmulticast_parameters;/* ##michal- this field has chenged to - "IBUD/IPv6_multicast_parameters" - gdror - this is OK for now */
pseudo_bit_tintr[0x0000a];/* MSI-X table entry index to be used to signal interrupts on this EQ. Reserved if MSI-X are not enabled in the PCI configuration header. */
pseudo_bit_treserved8[0x00016];
/* -------------- */
pseudo_bit_tmtt_base_addr_h[0x00008];/* MTT Base Address [39:32] relative to INIT_HCA.mtt_base_addr */
pseudo_bit_treserved9[0x00010];
pseudo_bit_tlog2_page_size[0x00006];/* Log (base 2) of MTT page size in units of 4KByte */
pseudo_bit_treserved10[0x00002];
/* -------------- */
pseudo_bit_treserved11[0x00003];
pseudo_bit_tmtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] relative to INIT_HCA.mtt_base_addr */
/* -------------- */
pseudo_bit_treserved12[0x00040];
/* -------------- */
pseudo_bit_tconsumer_counter[0x00018];/* Consumer counter. The counter is incremented for each EQE polled from the EQ.
Mustbe0x0inEQinitialization.
MaintainedbyHW(validfortheQUERY_EQcommandonly).*/
pseudo_bit_treserved13[0x00008];
/* -------------- */
pseudo_bit_tproducer_counter[0x00018];/* Producer Coutner. The counter is incremented for each EQE that is written by the HW to the EQ.
/* Memory Translation Table (MTT) Entry #### michal - match to PRM */
structhermonprm_mtt_st{/* Little Endian */
pseudo_bit_tptag_h[0x00020];/* High-order bits of physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */
/* -------------- */
pseudo_bit_tp[0x00001];/* Present bit. If set, page entry is valid. If cleared, access to this page will generate non-present page access fault. */
pseudo_bit_treserved0[0x00002];
pseudo_bit_tptag_l[0x0001d];/* Low-order bits of Physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */
/* -------------- */
};
/* Memory Protection Table (MPT) Entry ### doesn't match PRM (new fields were added). new size in bytes : 0x54 */
structhermonprm_mpt_st{/* Little Endian */
pseudo_bit_treserved0[0x00008];
pseudo_bit_tr_w[0x00001];/* Defines whether this entry is Region (1) or Window (0) */
pseudo_bit_tpa[0x00001];/* Physical address. If set, no virtual-to-physical address translation is performed for this region */
pseudo_bit_tlr[0x00001];/* If set - local read access is enabled. Must be set for all MPT Entries. */
pseudo_bit_tlw[0x00001];/* If set - local write access is enabled */
pseudo_bit_trr[0x00001];/* If set - remote read access is enabled. */
pseudo_bit_trw[0x00001];/* If set - remote write access is enabled */
pseudo_bit_tatomic[0x00001];/* If set - remote Atomic access is allowed. */
pseudo_bit_teb[0x00001];/* If set - bind is enabled. Valid only for regions. */
pseudo_bit_tatc_req[0x00001];/* If set, second hop of address translation (PA to MA) to be performed in the device prior to issuing the uplink request. */
pseudo_bit_tatc_xlated[0x00001];/* If set, uplink cycle to be issues with ATC_translated indicator to force bypass of the chipset IOMMU. */
pseudo_bit_treserved1[0x00001];
pseudo_bit_tno_snoop[0x00001];/* If set, issue PCIe cycle with ûno Snoopÿ attribute - cycle not to be snooped in CPU caches */
pseudo_bit_treserved2[0x00008];
pseudo_bit_tstatus[0x00004];/* 0xF - Not Valid 0x3 - Free. else - HW ownership.Unbound Type1 windows are denoted by reg_wnd_len=0. Unbound Type II windows are denoted by Status = Free. */
/* -------------- */
pseudo_bit_treserved3[0x00007];
pseudo_bit_tbqp[0x00001];/* 0 - not bound to qp (type 1 window, MR)1 - bound to qp (type 2 window) */
pseudo_bit_tqpn[0x00018];/* QP number this MW is attached to. Valid for type2 memory windows and on QUERY_MPT only */
/* -------------- */
pseudo_bit_tmem_key[0x00020];/* The memory Key. The field holds the mem_key field in the following semantics: {key[7:0],key[31:8]}. */
/* -------------- */
pseudo_bit_tpd[0x00018];/* Protection Domain. If VMM support is enabled PD[17:23] specify Guest VM Identifier */
pseudo_bit_tei[0x00001];/* Enable Invalidation - When set, Local/Remote invalidation can be executed on this window/region. Must be set for type2 windows and non-shared physical memory regions. Must be clear for regions that are used to access Work Queues, Completion Queues and Event Queues */
pseudo_bit_tnce[0x00001];/* Data can be cached in Network Cache (see ûNetwork Cacheÿ on page 81) */
pseudo_bit_tfre[0x00001];/* When set, Fast Registration Operations can be executed on this region */
pseudo_bit_trae[0x00001];/* When set, remote access can be enabled on this region. Used when executing Fast Registration Work Request to validate that remote access rights can be granted to this MPT. If the bit is cleared, Fast Registration Work Request requesting remote access rights will fail */
pseudo_bit_tw_dif[0x00001];/* Wire space contains dif */
pseudo_bit_tm_dif[0x00001];/* Memory space contains dif */
pseudo_bit_treserved4[0x00001];
/* -------------- */
pseudo_bit_tstart_addr_h[0x00020];/* Start Address - Virtual Address where this region/window starts */
/* -------------- */
pseudo_bit_tstart_addr_l[0x00020];/* Start Address - Virtual Address where this region/window starts */
pseudo_bit_tlkey[0x00020];/* Must be 0 for SW2HW_MPT. On QUERY_MPT and HW2SW_MPT commands for Memory Window it reflects the LKey of the Region that the Window is bound to.The field holds the lkey field in the following semantics: {key[7:0],key[31:8]}. */
/* -------------- */
pseudo_bit_twin_cnt[0x00018];/* Number of windows bound to this region. Valid for regions only.The field is valid only for the QUERY_MPT and HW2SW_MPT commands. */
pseudo_bit_treserved5[0x00008];
/* -------------- */
pseudo_bit_tmtt_rep[0x00004];/* Log (base 2) of the number of time an MTT is replicated.E.g. for 64KB virtual blocks from 512B blocks, a replication factor of 2^7 is needed (MTT_REPLICATION_FACTOR=7).Up to 1MB of replicated block works */
pseudo_bit_treserved6[0x00011];
pseudo_bit_tblock_mode[0x00001];/* If set, the page size is not power of two, and entity_size is in bytes. */
pseudo_bit_tlen64[0x00001];/* Region/Window Length[64]. This bit added to enable registering 2^64 bytes per region */
pseudo_bit_tfbo_en[0x00001];/* If set, mtt_fbo field is valid, otherwise it is calculated from least significant bytes of the address. Must be set when mtt_rep is used or MPT is block-mode region */
pseudo_bit_treserved7[0x00008];
/* -------------- */
pseudo_bit_tmtt_adr_h[0x00008];/* Offset to MTT list for this region. Must be aligned on 8 bytes. */
pseudo_bit_treserved8[0x00018];
/* -------------- */
pseudo_bit_tmtt_adr_l[0x00020];/* Offset to MTT list for this region. Must be aligned on 8 bytes.###michal-relpaced with: RESERVED .3;mtt_adr_l .29; gdror - this is OK to leave it this way. */
/* -------------- */
pseudo_bit_tmtt_size[0x00020];/* Number of MTT entries allocated for this MR.When Fast Registration Operations cannot be executed on this region (FRE bit is zero) this field is reserved.When Fast Registration Operation is enabled (FRE bit is set) this field indicates the number of MTTs allocated for this MR. If mtt_sz value cannot be zero. */
/* -------------- */
pseudo_bit_tentity_size[0x00015];/* Page/block size. If MPT maps pages, the page size is 2entiry_size. If MPT maps blocks, the entity_size field specifies block size in bytes. The minimum amount of memory that can be mapped with single MTT is 512 bytes. */
pseudo_bit_treserved9[0x0000b];
/* -------------- */
pseudo_bit_tmtt_fbo[0x00015];/* First byte offset in the zero-based region - the first byte within the first block/page start address refers to. When mtt_rep is being used, fbo points within the replicated block (i.e. block-size x 2^mtt_rep) */
pseudo_bit_treserved10[0x0000b];
/* -------------- */
};
/* Completion Queue Context Table Entry #### michal - match PRM */
structhermonprm_completion_queue_context_st{/* Little Endian */
pseudo_bit_treserved0[0x00008];
pseudo_bit_tst[0x00004];/* Event delivery state machine
0x0-reserved
0x9-ARMED(RequestforNotification)
0x6-ARMEDSOLICITED(RequestSolicitedNotification)
0xA-FIRED
other-reserved
Mustbe0x0inCQinitialization.
ValidfortheQUERY_CQandHW2SW_CQcommandsonly.*/
pseudo_bit_treserved1[0x00005];
pseudo_bit_toi[0x00001];/* When set, overrun ignore is enabled.
pseudo_bit_tstatus[0x00010];/* PCI Status Register */
/* -------------- */
pseudo_bit_trevision_id[0x00008];
pseudo_bit_tclass_code_hca_class_code[0x00018];
/* -------------- */
pseudo_bit_tcache_line_size[0x00008];/* Cache Line Size */
pseudo_bit_tlatency_timer[0x00008];
pseudo_bit_theader_type[0x00008];/* hardwired to zero */
pseudo_bit_tbist[0x00008];
/* -------------- */
pseudo_bit_tbar0_ctrl[0x00004];/* hard-wired to 0100 */
pseudo_bit_treserved0[0x00010];
pseudo_bit_tbar0_l[0x0000c];/* Lower bits of BAR0 (Device Configuration Space) */
/* -------------- */
pseudo_bit_tbar0_h[0x00020];/* Upper 32 bits of BAR0 (Device Configuration Space) */
/* -------------- */
pseudo_bit_tbar1_ctrl[0x00004];/* Hardwired to 1100 */
pseudo_bit_treserved1[0x00010];
pseudo_bit_tbar1_l[0x0000c];/* Lower bits of BAR1 (User Access Region - UAR - space) */
/* -------------- */
pseudo_bit_tbar1_h[0x00020];/* upper 32 bits of BAR1 (User Access Region - UAR - space) */
/* -------------- */
pseudo_bit_tbar2_ctrl[0x00004];/* Hardwired to 1100 */
pseudo_bit_treserved2[0x00010];
pseudo_bit_tbar2_l[0x0000c];/* Lower bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */
/* -------------- */
pseudo_bit_tbar2_h[0x00020];/* Upper 32 bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */
/* -------------- */
pseudo_bit_tcardbus_cis_pointer[0x00020];
/* -------------- */
pseudo_bit_tsubsystem_vendor_id[0x00010];/* Specified by the device NVMEM configuration */
pseudo_bit_tsubsystem_id[0x00010];/* Specified by the device NVMEM configuration */
/* -------------- */
pseudo_bit_texpansion_rom_enable[0x00001];/* Expansion ROM Enable. Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */
pseudo_bit_treserved3[0x0000a];
pseudo_bit_texpansion_rom_base_address[0x00015];/* Expansion ROM Base Address (upper 21 bit). Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */
/* -------------- */
pseudo_bit_tcapabilities_pointer[0x00008];/* Specified by the device NVMEM configuration */
pseudo_bit_treserved4[0x00018];
/* -------------- */
pseudo_bit_treserved5[0x00020];
/* -------------- */
pseudo_bit_tinterrupt_line[0x00008];
pseudo_bit_tinterrupt_pin[0x00008];
pseudo_bit_tmin_gnt[0x00008];
pseudo_bit_tmax_latency[0x00008];
/* -------------- */
pseudo_bit_treserved6[0x00100];
/* -------------- */
pseudo_bit_tmsi_cap_id[0x00008];
pseudo_bit_tmsi_next_cap_ptr[0x00008];
pseudo_bit_tmsi_en[0x00001];
pseudo_bit_tmultiple_msg_cap[0x00003];
pseudo_bit_tmultiple_msg_en[0x00003];
pseudo_bit_tcap_64_bit_addr[0x00001];
pseudo_bit_treserved7[0x00008];
/* -------------- */
pseudo_bit_tmsg_addr_l[0x00020];
/* -------------- */
pseudo_bit_tmsg_addr_h[0x00020];
/* -------------- */
pseudo_bit_tmsg_data[0x00010];
pseudo_bit_treserved8[0x00010];
/* -------------- */
pseudo_bit_treserved9[0x00080];
/* -------------- */
pseudo_bit_tpm_cap_id[0x00008];/* Power management capability ID - 01h */
pseudo_bit_tpm_next_cap_ptr[0x00008];
pseudo_bit_tpm_cap[0x00010];/* [2:0] Version - 02h
[3]PMEclock-0h
[4]RsvP
[5]Devicespecificinitialization-0h
[8:6]AUXcurrent-0h
[9]D1support-0h
[10]D2support-0h
[15:11]PMEsupport-0h*/
/* -------------- */
pseudo_bit_tpm_status_control[0x00010];/* [14:13] - Data scale - 0h */
pseudo_bit_tpm_control_status_brdg_ext[0x00008];
pseudo_bit_tdata[0x00008];
/* -------------- */
pseudo_bit_treserved10[0x00040];
/* -------------- */
pseudo_bit_tvpd_cap_id[0x00008];/* 03h */
pseudo_bit_tvpd_next_cap_id[0x00008];
pseudo_bit_tvpd_address[0x0000f];
pseudo_bit_tf[0x00001];
/* -------------- */
pseudo_bit_tvpd_data[0x00020];
/* -------------- */
pseudo_bit_treserved11[0x00040];
/* -------------- */
pseudo_bit_tpciex_cap_id[0x00008];/* PCI-Express capability ID - 10h */
pseudo_bit_tpciex_next_cap_ptr[0x00008];
pseudo_bit_tpciex_cap[0x00010];/* [3:0] Capability version - 1h
structhermonprm_page_fault_event_data_st{/* Little Endian */
pseudo_bit_tva_h[0x00020];/* Virtual Address[63:32] this page fault is reported on */
/* -------------- */
pseudo_bit_tva_l[0x00020];/* Virtual Address[63:32] this page fault is reported on */
/* -------------- */
pseudo_bit_tmem_key[0x00020];/* Memory Key this page fault is reported on */
/* -------------- */
pseudo_bit_tqp[0x00018];/* QP this page fault is reported on */
pseudo_bit_treserved0[0x00003];
pseudo_bit_ta[0x00001];/* If set the memory access that caused the page fault was atomic */
pseudo_bit_tlw[0x00001];/* If set the memory access that caused the page fault was local write */
pseudo_bit_tlr[0x00001];/* If set the memory access that caused the page fault was local read */
pseudo_bit_trw[0x00001];/* If set the memory access that caused the page fault was remote write */
pseudo_bit_trr[0x00001];/* If set the memory access that caused the page fault was remote read */
/* -------------- */
pseudo_bit_tpd[0x00018];/* PD this page fault is reported on */
pseudo_bit_treserved1[0x00008];
/* -------------- */
pseudo_bit_tprefetch_len[0x00020];/* Indicates how many subsequent pages in the same memory region/window will be accessed by the following transaction after this page fault is resolved. measured in bytes. SW can use this information in order to page-in the subsequent pages if they are not present. */
/* -------------- */
};
/* WQE segments format */
structhermonprm_wqe_segment_st{/* Little Endian */
structhermonprm_send_wqe_segment_stsend_wqe_segment;/* Send WQE segment format */
/* -------------- */
pseudo_bit_treserved0[0x00280];
/* -------------- */
structhermonprm_wqe_segment_ctrl_mlx_stmlx_wqe_segment_ctrl;/* MLX WQE segment format */
/* -------------- */
pseudo_bit_treserved1[0x00100];
/* -------------- */
pseudo_bit_trecv_wqe_segment_ctrl[4][0x00020];/* Receive segment format */
/* -------------- */
pseudo_bit_treserved2[0x00080];
/* -------------- */
};
/* Event_data Field - Port State Change #### michal - match PRM */
structhermonprm_port_state_change_st{/* Little Endian */
pseudo_bit_treserved0[0x00040];
/* -------------- */
pseudo_bit_treserved1[0x0001c];
pseudo_bit_tp[0x00002];/* Port number (1 or 2) */
pseudo_bit_treserved2[0x00002];
/* -------------- */
pseudo_bit_treserved3[0x00060];
/* -------------- */
};
/* Event_data Field - Completion Queue Error #### michal - match PRM */
structhermonprm_completion_queue_error_st{/* Little Endian */
pseudo_bit_tcqn[0x00018];/* CQ number event is reported for */
pseudo_bit_treserved0[0x00008];
/* -------------- */
pseudo_bit_treserved1[0x00020];
/* -------------- */
pseudo_bit_tsyndrome[0x00008];/* Error syndrome
0x01-CQoverrun
0x02-CQaccessviolationerror*/
pseudo_bit_treserved2[0x00018];
/* -------------- */
pseudo_bit_treserved3[0x00060];
/* -------------- */
};
/* Event_data Field - Completion Event #### michal - match PRM */
structhermonprm_completion_event_st{/* Little Endian */
pseudo_bit_tcqn[0x00018];/* CQ number event is reported for */
pseudo_bit_treserved0[0x00008];
/* -------------- */
pseudo_bit_treserved1[0x000a0];
/* -------------- */
};
/* Event Queue Entry #### michal - match to PRM */
structhermonprm_event_queue_entry_st{/* Little Endian */
pseudo_bit_tevent_sub_type[0x00008];/* Event Sub Type.
pseudo_bit_tevent_data[6][0x00020];/* Delivers auxilary data to handle event. */
/* -------------- */
pseudo_bit_treserved2[0x00007];
pseudo_bit_towner[0x00001];/* Owner of the entry
0SW
1HW*/
pseudo_bit_treserved3[0x00018];
/* -------------- */
};
/* QP/EE State Transitions Command Parameters ###michal - doesn't match PRM (field name changed) */
structhermonprm_qp_ee_state_transitions_st{/* Little Endian */
pseudo_bit_topt_param_mask[0x00020];/* This field defines which optional parameters are passed. Each bit specifies whether optional parameter is passed (set) or not (cleared). The optparammask is defined for each QP/EE command. */
/* -------------- */
pseudo_bit_treserved0[0x00020];
/* -------------- */
structhermonprm_queue_pair_ee_context_entry_stqpc_eec_data;/* QPC/EEC data ###michal - field has replaced with "qpc_data" (size .1948) */
/* -------------- */
pseudo_bit_treserved1[0x00800];
/* -------------- */
};
/* Completion Queue Entry Format #### michal - fixed by gdror */
structhermonprm_completion_queue_entry_st{/* Little Endian */
pseudo_bit_tqpn[0x00018];/* Indicates the QP for which completion is being reported */
pseudo_bit_treserved0[0x00002];
pseudo_bit_td2s[0x00001];/* Duplicate to Sniffer. This bit is set if both Send and Receive queues are subject for sniffer queue. The HW delivers
packetonlytosend-associatedsnifferreceivequeue.*/
pseudo_bit_tfcrc_sd[0x00001];/* FCRC: If set, FC CRC is correct in FC frame encapsulated in payload. Valid for Raw Frame FC receive queue only.
pseudo_bit_tfl[0x00001];/* Force Loopback Valid for responder RawEth and UD only. */
pseudo_bit_tvlan[0x00002];/* Valid for RawEth and UD over Ethernet only. Applicable for RawEth and UD over Ethernet Receive queue
00-NoVLANheaderwaspresentinthepacket
01-C-VLAN(802.1q)Headerwaspresentintheframe.
10-S-VLAN(802.1ad)Headerwaspresentintheframe.*/
pseudo_bit_tdife[0x00001];/* DIF Error */
/* -------------- */
pseudo_bit_timmediate_rssvalue_invalidatekey[0x00020];/* For a responder CQE, if completed WQE Opcode is Send With Immediate or Write With Immediate, this field contains immediate field of the received message.
pseudo_bit_tsrq_rqpn[0x00018];/* For Responder UD QPs, Remote (source) QP number.
ForResponderSRCQPs,SRQnumber.
Otherwise,thisfieldisreserved.*/
pseudo_bit_tml_path_mac_index[0x00007];/* For responder UD over IB CQE: These are the lower LMC bits of the DLID in an incoming UD packet, higher bits of this field, that are not part of the LMC bits are zeroed by HW. Invalid if incoming message DLID is the permissive LID or incoming message is multicast.
pseudo_bit_terr_ba[0x00002];/* Error bank address */
pseudo_bit_treserved3[0x00011];
pseudo_bit_toverflow[0x00001];/* Fatal: ECC error FIFO overflow - ECC errors were detected, which may or may not have been corrected by InfiniHost-III-EX */
