structarbelprm_send_doorbell_st{/* Little Endian */
pseudo_bit_tnopcode[0x00005];/* Opcode of descriptor to be executed */
pseudo_bit_tf[0x00001];/* Fence bit. If set, descriptor is fenced */
pseudo_bit_treserved0[0x00002];
pseudo_bit_twqe_counter[0x00010];/* Modulo-64K counter of WQEs posted to the QP since its creation excluding the newly posted WQEs in this doorbell. Should be zero for the first doorbell on the QP */
pseudo_bit_twqe_cnt[0x00008];/* Number of WQEs posted with this doorbell. Must be grater then zero. */
/* -------------- */
pseudo_bit_tnds[0x00006];/* Next descriptor size (in 16-byte chunks) */
pseudo_bit_treserved1[0x00002];
pseudo_bit_tqpn[0x00018];/* QP number this doorbell is rung on */
structarbelprm_wqe_segment_ctrl_send_st{/* Little Endian */
pseudo_bit_talways1[0x00001];
pseudo_bit_ts[0x00001];/* Solicited Event bit. If set, SE (Solicited Event) bit is set in the (last packet of) message. */
pseudo_bit_te[0x00001];/* Event bit. If set, event is generated upon WQE?s completion, if QP is allowed to generate an event. Every WQE with E-bit set generates an event. The C bit must be set on unsignalled QPs if the E bit is set. */
pseudo_bit_tc[0x00001];/* Completion Queue bit. Valid for unsignalled QPs only. If set, the CQ is updated upon WQE?s completion */
pseudo_bit_tip[0x00001];/* When set, InfiniHost III Ex will calculate the IP checksum of the IP header that is present immediately after the IPoverIB encapsulation header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first IP header following the IPoverIB encapsulation header. Not Valid for IPv6 packets */
pseudo_bit_ttcp_udp[0x00001];/* When set, InfiniHost III Ex will calculate the TCP/UDP checksum of the packet that is present immediately after the IP header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first TCP header following the IP header. This bit may be set only if the entire TCP/UDP segment is present in one IB packet */
pseudo_bit_treserved0[0x00001];
pseudo_bit_tso[0x00001];/* Strong Ordering - when set, the WQE will be executed only after all previous WQEs have been executed. Can be set for RC WQEs only. This bit must be set in type two BIND, Fast Registration and Local invalidate operations. */
pseudo_bit_treserved1[0x00018];
/* -------------- */
pseudo_bit_timmediate[0x00020];/* If the OpCode encodes an operation with Immediate (RDMA-write/SEND), This field will hold the Immediate data to be sent. If the OpCode encodes send and invalidate operations, this field holds the Invalidation key to be inserted into the packet; otherwise, this field is reserved. */
structarbelprm_wqe_segment_next_st{/* Little Endian */
pseudo_bit_tnopcode[0x00005];/* Next Opcode: OpCode to be used in the next WQE. Encodes the type of operation to be executed on the QP:
?00000? - NOP. WQE with this opcode creates a completion, but does nothing else
?01000? - RDMA-write
?01001? - RDMA-Write with Immediate
?10000? - RDMA-read
?10001? - Atomic Compare & swap
?10010? - Atomic Fetch & Add
?11000? - Bind memory window
The encoding for the following operations depends on the QP type:
For RC, UC and RD QP:
?01010? - SEND
?01011? - SEND with Immediate
For UD QP:
the encoding depends on the values of bit[31] of the Q_key field in the Datagram Segment (see Table 39, ?Unreliable Datagram Segment Format - Pointers,? on page 101) of
both the current WQE and the next WQE, as follows:
If the last WQE Q_Key bit[31] is clear and the next WQE Q_key bit[31] is set :
?01000? - SEND
?01001? - SEND with Immediate
otherwise (if the next WQE Q_key bit[31] is cleared, or the last WQE Q_Key bit[31] is set):
?01010? - SEND
?01011? - SEND with Immediate
All other opcode values are RESERVED, and will result in invalid operation execution. */
pseudo_bit_treserved0[0x00001];
pseudo_bit_tnda_31_6[0x0001a];/* Next WQE address, low 32 bit. WQE address must be aligned to 64-byte boundary (6 LSB are forced ZERO). */
/* -------------- */
pseudo_bit_tnds[0x00006];/* Next WQE size in OctoWords (16 bytes).
Zero value in NDS field signals end of WQEs? chain.
*/
pseudo_bit_tf[0x00001];/* Fence bit. If set, next WQE will start execution only after all previous Read/Atomic WQEs complete. */
structarbelprm_address_path_st{/* Little Endian */
pseudo_bit_tpkey_index[0x00007];/* PKey table index */
pseudo_bit_treserved0[0x00011];
pseudo_bit_tport_number[0x00002];/* Specific port associated with this QP/EE.
1 - Port 1
2 - Port 2
other - reserved */
pseudo_bit_treserved1[0x00006];
/* -------------- */
pseudo_bit_trlid[0x00010];/* Remote (Destination) LID */
pseudo_bit_tmy_lid_path_bits[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */
pseudo_bit_tg[0x00001];/* Global address enable - if set, GRH will be formed for packet header */
pseudo_bit_treserved2[0x00005];
pseudo_bit_trnr_retry[0x00003];/* RNR retry count (see C9-132 in IB spec Vol 1)
0-6 - number of retries
7 - infinite */
/* -------------- */
pseudo_bit_thop_limit[0x00008];/* IPv6 hop limit */
pseudo_bit_tmax_stat_rate[0x00003];/* Maximum static rate control.
0 - 100% injection rate
1 - 25% injection rate
2 - 12.5% injection rate
3 - 50% injection rate
other - reserved */
pseudo_bit_treserved3[0x00005];
pseudo_bit_tmgid_index[0x00006];/* Index to port GID table */
pseudo_bit_treserved4[0x00005];
pseudo_bit_tack_timeout[0x00005];/* Local ACK timeout - Transport timer for activation of retransmission mechanism. Refer to IB spec Vol1 9.7.6.1.3 for further details.
The transport timer is set to 4.096us*2^ack_timeout, if ack_timeout is 0 then transport timer is disabled. */
pseudo_bit_tout_param_h[0x00020];/* Output Parameter: parameter[63:32] or pointer[63:32] to output mailbox (see command description) */
/* -------------- */
pseudo_bit_tout_param_l[0x00020];/* Output Parameter: parameter[31:0] or pointer[31:0] to output mailbox (see command description) */
/* -------------- */
pseudo_bit_treserved0[0x00010];
pseudo_bit_ttoken[0x00010];/* Software assigned token to the command, to uniquely identify it. The token is returned to the software in the EQE reported. */
/* -------------- */
pseudo_bit_topcode[0x0000c];/* Command opcode */
pseudo_bit_topcode_modifier[0x00004];/* Opcode Modifier, see specific description for each command. */
pseudo_bit_treserved1[0x00006];
pseudo_bit_te[0x00001];/* Event Request
0 - Don't report event (software will poll the GO bit)
1 - Report event to EQ when the command completes */
pseudo_bit_tgo[0x00001];/* Go (0=Software ownership for the HCR, 1=Hardware ownership for the HCR)
Software can write to the HCR only if Go bit is cleared.
Software must set the Go bit to trigger the HW to execute the command. Software must not write to this register value other than 1 for the Go bit. */
pseudo_bit_tstatus[0x00008];/* Command execution status report. Valid only if command interface in under SW ownership (Go bit is cleared)
0 - command completed without error. If different than zero, command execution completed with error. Syndrom encoding is depended on command executed and is defined for each command */
structarbelprm_cq_cmd_doorbell_st{/* Little Endian */
pseudo_bit_tcqn[0x00018];/* CQ number accessed */
pseudo_bit_tcmd[0x00003];/* Command to be executed on CQ
0x0 - Reserved
0x1 - Request notification for next Solicited completion event. CQ_param specifies the current CQ Consumer Counter.
0x2 - Request notification for next Solicited or Unsolicited completion event. CQ_param specifies the current CQ Consumer Counter.
0x3 - Request notification for multiple completions (Arm-N). CQ_param specifies the value of the CQ Counter that when reached by HW (i.e. HW generates a CQE into this Counter) Event will be generated
Other - Reserved */
pseudo_bit_treserved0[0x00001];
pseudo_bit_tcmd_sn[0x00002];/* Command Sequence Number - This field should be incremented upon receiving completion notification of the respective CQ.
This transition is done by ringing Request notification for next Solicited, Request notification for next Solicited or Unsolicited
completion or Request notification for multiple completions doorbells after receiving completion notification.
This field is initialized to Zero */
pseudo_bit_treserved1[0x00002];
/* -------------- */
pseudo_bit_tcq_param[0x00020];/* parameter to be used by CQ command */
pseudo_bit_tqpn_i[0x00018];/* QPN_i: QP number which is a member in this multicast group. Valid only if Qi bit is set. Length of the QPN_i list is set in INIT_HCA */
pseudo_bit_tf0[0x00001];/* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */
pseudo_bit_tf1[0x00001];/* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */
pseudo_bit_tf2[0x00001];/* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */
pseudo_bit_treserved3[0x00001];
pseudo_bit_tev_cnt1[0x00005];/* Specifies event to be counted by Event_counter1 See XXX for events' definition. */
pseudo_bit_treserved4[0x00003];
pseudo_bit_tev_cnt2[0x00005];/* Specifies event to be counted by Event_counter2 See XXX for events' definition. */
pseudo_bit_treserved5[0x00003];
/* -------------- */
pseudo_bit_tclock_counter[0x00020];
/* -------------- */
pseudo_bit_tevent_counter1[0x00020];
/* -------------- */
pseudo_bit_tevent_counter2[0x00020];/* Read/write event counter, counting events specified by EvCntl and EvCnt2 fields repsectively. When the event counter reaches is maximum value of 0xFFFFFF, the next event will cause it to roll over to zero, set F1 or F2 bit respectively and generate interrupt by I1 I2 bit respectively. */
pseudo_bit_ticrc[0x00002];/* icrc field detemines what to do with the last dword of the packet: 0 - Calculate ICRC and put it instead of last dword. Last dword must be 0x0. 1,2 - reserved. 3 - Leave last dword as is. Last dword must not be 0x0. */
pseudo_bit_treserved1[0x00002];
pseudo_bit_tsl[0x00004];
pseudo_bit_tmax_statrate[0x00004];
pseudo_bit_tslr[0x00001];/* 0= take slid from port. 1= take slid from given headers */
pseudo_bit_tv15[0x00001];/* Send packet over VL15 */
pseudo_bit_treserved2[0x0000e];
/* -------------- */
pseudo_bit_tvcrc[0x00010];/* Packet's VCRC (if not 0 - otherwise computed by HW) */
pseudo_bit_trlid[0x00010];/* Destination LID (must match given headers) */
structarbelprm_queue_pair_ee_context_entry_st{/* Little Endian */
pseudo_bit_treserved0[0x00008];
pseudo_bit_tde[0x00001];/* Send/Receive Descriptor Event enable - if set, events can be generated upon descriptors' completion on send/receive queue (controlled by E bit in WQE). Invalid in EE context */
pseudo_bit_treserved1[0x00002];
pseudo_bit_tpm_state[0x00002];/* Path migration state (Migrated, Armed or Rearm)
11-Migrated
00-Armed
01-Rearm
10-Reserved
Should be set to 11 for UD QPs and for QPs which do not support APM */
pseudo_bit_treserved2[0x00003];
pseudo_bit_tst[0x00003];/* Service type (invalid in EE context):
000-Reliable Connection
001-Unreliable Connection
010-Reliable Datagram
011-Unreliable Datagram
111-MLX transport (raw bits injection). Used for management QPs and RAW */
pseudo_bit_treserved3[0x00009];
pseudo_bit_tstate[0x00004];/* QP/EE state:
0 - RST
1 - INIT
2 - RTR
3 - RTS
4 - SQEr
5 - SQD (Send Queue Drained)
6 - ERR
7 - Send Queue Draining
8 - Reserved
9 - Suspended
A- F - Reserved
(Valid for QUERY_QPEE and ERR2RST_QPEE commands only) */
/* -------------- */
pseudo_bit_treserved4[0x00020];
/* -------------- */
pseudo_bit_tsched_queue[0x00004];/* Schedule queue to be used for WQE scheduling to execution. Determines QOS for this QP. */
pseudo_bit_trlky[0x00001];/* When set this QP can use the Reserved L_Key */
pseudo_bit_treserved5[0x00003];
pseudo_bit_tlog_sq_stride[0x00003];/* Stride on the send queue. WQ entry is 16*(2^log_SQ_stride) bytes.
Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */
pseudo_bit_tlog_sq_size[0x00004];/* Log2 of the Number of WQEs in the Send Queue. */
pseudo_bit_treserved6[0x00001];
pseudo_bit_tlog_rq_stride[0x00003];/* Stride on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes.
Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */
pseudo_bit_tlog_rq_size[0x00004];/* Log2 of the Number of WQEs in the Receive Queue. */
pseudo_bit_treserved7[0x00001];
pseudo_bit_tmsg_max[0x00005];/* Max message size allowed on the QP. Maximum message size is 2^msg_Max.
Must be equal to MTU for UD and MLX QPs. */
pseudo_bit_tmtu[0x00003];/* MTU of the QP (Must be the same for both paths: primary and alternative):
0x1 - 256 bytes
0x2 - 512
0x3 - 1024
0x4 - 2048
other - reserved
Should be configured to 0x4 for UD and MLX QPs. */
/* -------------- */
pseudo_bit_tusr_page[0x00018];/* QP (see "non_privileged Access to the HCA Hardware"). Not valid (reserved) in EE context. */
pseudo_bit_treserved8[0x00008];
/* -------------- */
pseudo_bit_tlocal_qpn_een[0x00018];/* Local QP/EE number Lower bits determine position of this record in QPC table, and - thus - constrained
This field is valid for QUERY and ERR2RST commands only. */
pseudo_bit_treserved9[0x00008];
/* -------------- */
pseudo_bit_tremote_qpn_een[0x00018];/* Remote QP/EE number */
pseudo_bit_treserved10[0x00008];
/* -------------- */
pseudo_bit_treserved11[0x00040];
/* -------------- */
structarbelprm_address_path_stprimary_address_path;/* Primary address path for the QP/EE */
/* -------------- */
structarbelprm_address_path_stalternative_address_path;/* Alternate address path for the QP/EE */
0 - only send WQEs with C bit set generate completion.
Not valid (reserved) in EE context. */
pseudo_bit_tsic[0x00001];/* If set - Ignore end to end credits on send queue. Not valid (reserved) in EE context. */
pseudo_bit_tcur_retry_cnt[0x00003];/* Current transport retry counter (QUERY_QPEE only).
The current transport retry counter can vary from retry_count down to 1, where 1 means that the last retry attempt is currently executing. */
pseudo_bit_tcur_rnr_retry[0x00003];/* Current RNR retry counter (QUERY_QPEE only).
The current RNR retry counter can vary from rnr_retry to 1, where 1 means that the last retry attempt is currently executing. */
pseudo_bit_tfre[0x00001];/* Fast Registration Work Request Enabled. (Reserved for EE) */
pseudo_bit_treserved15[0x00001];
pseudo_bit_tsae[0x00001];/* If set - Atomic operations enabled on send queue. Not valid (reserved) in EE context. */
pseudo_bit_tswe[0x00001];/* If set - RDMA - write enabled on send queue. Not valid (reserved) in EE context. */
pseudo_bit_tsre[0x00001];/* If set - RDMA - read enabled on send queue. Not valid (reserved) in EE context. */
pseudo_bit_tretry_count[0x00003];/* Transport timeout Retry count */
pseudo_bit_treserved16[0x00002];
pseudo_bit_tsra_max[0x00003];/* Maximum number of outstanding RDMA-read/Atomic operations allowed in the send queue. Maximum number is 2^SRA_Max. Must be zero in EE context. */
pseudo_bit_tflight_lim[0x00004];/* Number of outstanding (in-flight) messages on the wire allowed for this send queue.
Number of outstanding messages is 2^Flight_Lim.
Use 0xF for unlimited number of outstanding messages. */
pseudo_bit_tack_req_freq[0x00004];/* ACK required frequency. ACK required bit will be set in every 2^AckReqFreq packets at least. Not valid for RD QP. */
/* -------------- */
pseudo_bit_treserved17[0x00020];
/* -------------- */
pseudo_bit_tnext_send_psn[0x00018];/* Next PSN to be sent */
pseudo_bit_treserved18[0x00008];
/* -------------- */
pseudo_bit_tcqn_snd[0x00018];/* CQ number completions from the send queue to be reported to. Not valid (reserved) in EE context. */
pseudo_bit_treserved19[0x00008];
/* -------------- */
pseudo_bit_treserved20[0x00006];
pseudo_bit_tsnd_wqe_base_adr_l[0x0001a];/* While opening (creating) the WQ, this field should contain the address of first descriptor to be posted. Not valid (reserved) in EE context. */
/* -------------- */
pseudo_bit_tsnd_db_record_index[0x00020];/* Index in the UAR Context Table Entry.
HW uses this index as an offset from the UAR Context Table Entry in order to read this SQ doorbell record.
The entry is obtained via the usr_page field.
Not valid for EE. */
/* -------------- */
pseudo_bit_tlast_acked_psn[0x00018];/* The last acknowledged PSN for the requester (QUERY_QPEE only) */
pseudo_bit_treserved21[0x00008];
/* -------------- */
pseudo_bit_tssn[0x00018];/* Requester Send Sequence Number (QUERY_QPEE only) */
pseudo_bit_treserved22[0x00008];
/* -------------- */
pseudo_bit_treserved23[0x00003];
pseudo_bit_trsc[0x00001];/* 1 - all receive WQEs generate CQEs.
0 - only receive WQEs with C bit set generate completion.
Not valid (reserved) in EE context.
*/
pseudo_bit_tric[0x00001];/* Invalid Credits.
1 - place "Invalid Credits" to ACKs sent from this queue.
0 - ACKs report the actual number of end to end credits on the connection.
Not valid (reserved) in EE context.
Must be set to 1 on QPs which are attached to SRQ. */
pseudo_bit_treserved24[0x00008];
pseudo_bit_trae[0x00001];/* If set - Atomic operations enabled. on receive queue. Not valid (reserved) in EE context. */
pseudo_bit_trwe[0x00001];/* If set - RDMA - write enabled on receive queue. Not valid (reserved) in EE context. */
pseudo_bit_trre[0x00001];/* If set - RDMA - read enabled on receive queue. Not valid (reserved) in EE context. */
pseudo_bit_treserved25[0x00005];
pseudo_bit_trra_max[0x00003];/* Maximum number of outstanding RDMA-read/Atomic operations allowed on receive queue is 2^RRA_Max.
Must be 0 for EE context. */
pseudo_bit_treserved26[0x00008];
/* -------------- */
pseudo_bit_tnext_rcv_psn[0x00018];/* Next (expected) PSN on receive */
pseudo_bit_tmin_rnr_nak[0x00005];/* Minimum RNR NAK timer value (TTTTT field encoding according to the IB spec Vol1 9.7.5.2.8).
Not valid (reserved) in EE context. */
pseudo_bit_treserved27[0x00003];
/* -------------- */
pseudo_bit_treserved28[0x00005];
pseudo_bit_tra_buff_indx[0x0001b];/* Index to outstanding read/atomic buffer.
This field constructs the address to the RDB for maintaining the incoming RDMA read and atomic requests. */
/* -------------- */
pseudo_bit_tcqn_rcv[0x00018];/* CQ number completions from receive queue to be reported to. Not valid (reserved) in EE context. */
pseudo_bit_treserved29[0x00008];
/* -------------- */
pseudo_bit_treserved30[0x00006];
pseudo_bit_trcv_wqe_base_adr_l[0x0001a];/* While opening (creating) the WQ, this field should contain the address of first descriptor to be posted. Not valid (reserved) in EE context. */
/* -------------- */
pseudo_bit_trcv_db_record_index[0x00020];/* Index in the UAR Context Table Entry containing the doorbell record for the receive queue.
HW uses this index as an offset from the UAR Context Table Entry in order to read this RQ doorbell record.
The entry is obtained via the usr_page field.
Not valid for EE. */
/* -------------- */
pseudo_bit_tq_key[0x00020];/* Q_Key to be validated against received datagrams.
On send datagrams, if Q_Key[31] specified in the WQE is set, then this Q_Key will be transmitted in the outgoing message.
Not valid (reserved) in EE context. */
/* -------------- */
pseudo_bit_tsrqn[0x00018];/* SRQN - Shared Receive Queue Number - specifies the SRQ number from which the QP dequeues receive descriptors.
SRQN is valid only if SRQ bit is set. Not valid (reserved) in EE context. */
pseudo_bit_tsrq[0x00001];/* SRQ - Shared Receive Queue. If this bit is set, then the QP is associated with a SRQ. Not valid (reserved) in EE context. */
pseudo_bit_treserved31[0x00007];
/* -------------- */
pseudo_bit_trmsn[0x00018];/* Responder current message sequence number (QUERY_QPEE only) */
pseudo_bit_treserved32[0x00008];
/* -------------- */
pseudo_bit_tsq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the SQ.
Must be 0x0 in SQ initialization.
(QUERY_QPEE only). */
pseudo_bit_trq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the RQ.
Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot.
This register is write-only. Reading from this register will cause undefined result
Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot.
This register is write-only. Reading from this register will cause undefined result */
structarbelprm_cq_arm_db_record_st{/* Little Endian */
pseudo_bit_tcounter[0x00020];/* CQ counter for the arming request */
/* -------------- */
pseudo_bit_tcmd[0x00003];/* 0x0 - No command
0x1 - Request notification for next Solicited completion event. Counter filed specifies the current CQ Consumer Counter.
0x2 - Request notification for next Solicited or Unsolicited completion event. Counter filed specifies the current CQ Consumer counter.
0x3 - Request notification for multiple completions (Arm-N). Counter filed specifies the value of the CQ Index that when reached by HW (i.e. HW generates a CQE into this Index) Event will be generated
Other - Reserved */
pseudo_bit_tcmd_sn[0x00002];/* Command Sequence Number - See Table 35, "CQ Doorbell Layout" for definition of this filed */
pseudo_bit_tlog_srq_size[0x00004];/* Log2 of the Number of WQEs in the Receive Queue.
Maximum value is 0x10, i.e. 16M WQEs. */
pseudo_bit_tstate[0x00004];/* SRQ State:
1111 - SW Ownership
0000 - HW Ownership
0001 - Error
Valid only on QUERY_SRQ and HW2SW_SRQ commands. */
/* -------------- */
pseudo_bit_tl_key[0x00020];/* memory key (L-Key) to be used to access WQEs. */
/* -------------- */
pseudo_bit_tsrq_db_record_index[0x00020];/* Index in the UAR Context Table Entry containing the doorbell record for the receive queue.
HW uses this index as an offset from the UAR Context Table Entry in order to read this SRQ doorbell record.
The entry is obtained via the usr_page field. */
/* -------------- */
pseudo_bit_tusr_page[0x00018];/* Index (offset) of user page allocated for this SRQ (see "non_privileged Access to the HCA Hardware"). Not valid (reserved) in EE context. */
pseudo_bit_treserved0[0x00005];
pseudo_bit_tlog_rq_stride[0x00003];/* Stride (max WQE size) on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes. */
/* -------------- */
pseudo_bit_twqe_addr_h[0x00020];/* Bits 63:32 of WQE address (WQE base address) */
/* -------------- */
pseudo_bit_treserved1[0x00006];
pseudo_bit_tsrq_wqe_base_adr_l[0x0001a];/* While opening (creating) the SRQ, this field should contain the address of first descriptor to be posted. */
pseudo_bit_twqe_cnt[0x00010];/* WQE count on the SRQ.
Valid only on QUERY_SRQ and HW2SW_SRQ commands. */
pseudo_bit_tlwm[0x00010];/* Limit Water Mark - if the LWM is not zero, and the wqe_cnt drops below LWM when a WQE is dequeued from the SRQ, then a SRQ limit event is fired and the LWM is set to zero. */
/* -------------- */
pseudo_bit_tsrq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the SQ.
structarbelprm_completion_with_error_st{/* Little Endian */
pseudo_bit_tmyqpn[0x00018];/* Indicates the QP for which completion is being reported */
pseudo_bit_treserved0[0x00008];
/* -------------- */
pseudo_bit_treserved1[0x00060];
/* -------------- */
pseudo_bit_treserved2[0x00010];
pseudo_bit_tvendor_code[0x00008];
pseudo_bit_tsyndrome[0x00008];/* Completion with error syndrome:
0x01 - Local Length Error
0x02 - Local QP Operation Error
0x03 - Local EE Context Operation Error
0x04 - Local Protection Error
0x05 - Work Request Flushed Error
0x06 - Memory Window Bind Error
0x10 - Bad Response Error
0x11 - Local Access Error
0x12 - Remote Invalid Request Error
0x13 - Remote Access Error
0x14 - Remote Operation Error
0x15 - Transport Retry Counter Exceeded
0x16 - RNR Retry Counter Exceeded
0x20 - Local RDD Violation Error
0x21 - Remote Invalid RD Request
0x22 - Remote Aborted Error
0x23 - Invalid EE Context Number
0x24 - Invalid EE Context State
other - Reserved
Syndrome is defined according to the IB specification volume 1. For detailed explanation of the syndromes, refer to chapters 10-11 of the IB specification rev 1.1. */
/* -------------- */
pseudo_bit_treserved3[0x00020];
/* -------------- */
pseudo_bit_treserved4[0x00006];
pseudo_bit_twqe_addr[0x0001a];/* Bits 31:6 of WQE virtual address completion is reported for. The 6 least significant bits are zero. */
/* -------------- */
pseudo_bit_treserved5[0x00007];
pseudo_bit_towner[0x00001];/* Owner field. Zero value of this field means SW ownership of CQE. */
pseudo_bit_treserved6[0x00010];
pseudo_bit_topcode[0x00008];/* The opcode of WQE completion is reported for.
The following values are reported in case of completion with error:
0xFE - For completion with error on Receive Queues
0xFF - For completion with error on Send Queues */
structarbelprm_mad_ifc_input_modifier_st{/* Little Endian */
pseudo_bit_tport_number[0x00008];/* The packet reception port number (1 or 2). */
pseudo_bit_tmad_extended_info[0x00001];/* Mad_Extended_Info valid bit (MAD_IFC Input Mailbox data from offset 00100h and down). MAD_Extended_Info is read only if this bit is set.
Required for trap generation when BKey check is enabled and for global routed packets. */
pseudo_bit_treserved0[0x00007];
pseudo_bit_trlid[0x00010];/* Remote (source) LID from the received MAD.
This field is required for trap generation upon MKey/BKey validation. */
structarbelprm_query_debug_msg_st{/* Little Endian */
pseudo_bit_tphy_addr_h[0x00020];/* Translation of the address in firmware area. High 32 bits. */
/* -------------- */
pseudo_bit_tv[0x00001];/* Physical translation is valid */
pseudo_bit_treserved0[0x0000b];
pseudo_bit_tphy_addr_l[0x00014];/* Translation of the address in firmware area. Low 32 bits. */
/* -------------- */
pseudo_bit_tfw_area_base[0x00020];/* Firmware area base address. The format strings and the trace buffers may be located starting from this address. */
/* -------------- */
pseudo_bit_tfw_area_size[0x00020];/* Firmware area size */
/* -------------- */
pseudo_bit_ttrc_hdr_sz[0x00020];/* Trace message header size in dwords. */
/* -------------- */
pseudo_bit_ttrc_arg_num[0x00020];/* The number of arguments per trace message. */
structarbelprm_receive_doorbell_st{/* Little Endian */
pseudo_bit_treserved0[0x00008];
pseudo_bit_twqe_counter[0x00010];/* Modulo-64K counter of WQEs posted on this queue since its creation. Should be zero for the first doorbell on the QP */
pseudo_bit_treserved1[0x00008];
/* -------------- */
pseudo_bit_treserved2[0x00005];
pseudo_bit_tsrq[0x00001];/* If set, this is a Shared Receive Queue */
pseudo_bit_treserved3[0x00002];
pseudo_bit_tqpn[0x00018];/* QP number or SRQ number this doorbell is rung on */
structarbelprm_query_dev_lim_st{/* Little Endian */
pseudo_bit_treserved0[0x00080];
/* -------------- */
pseudo_bit_tlog_max_qp[0x00005];/* Log2 of the Maximum number of QPs supported */
pseudo_bit_treserved1[0x00003];
pseudo_bit_tlog2_rsvd_qps[0x00004];/* Log (base 2) of the number of QPs reserved for firmware use
The reserved resources are numbered from 0 to 2^log2_rsvd_qps-1 */
pseudo_bit_treserved2[0x00004];
pseudo_bit_tlog_max_qp_sz[0x00008];/* The maximum number of WQEs allowed on the RQ or the SQ is 2^log_max_qp_sz-1 */
pseudo_bit_tlog_max_srq_sz[0x00008];/* The maximum number of WQEs allowed on the SRQ is 2^log_max_srq_sz-1 */
/* -------------- */
pseudo_bit_tlog_max_ee[0x00005];/* Log2 of the Maximum number of EE contexts supported */
pseudo_bit_treserved3[0x00003];
pseudo_bit_tlog2_rsvd_ees[0x00004];/* Log (base 2) of the number of EECs reserved for firmware use
The reserved resources are numbered from 0 to 2^log2_rsvd_ees-1 */
pseudo_bit_treserved4[0x00004];
pseudo_bit_tlog_max_srqs[0x00005];/* Log base 2 of the maximum number of SRQs supported, valid only if SRQ bit is set.
*/
pseudo_bit_treserved5[0x00007];
pseudo_bit_tlog2_rsvd_srqs[0x00004];/* Log (base 2) of the number of reserved SRQs for firmware use
The reserved resources are numbered from 0 to 2^log2_rsvd_srqs-1
This parameter is valid only if the SRQ bit is set. */
/* -------------- */
pseudo_bit_tlog_max_cq[0x00005];/* Log2 of the Maximum number of CQs supported */
pseudo_bit_treserved6[0x00003];
pseudo_bit_tlog2_rsvd_cqs[0x00004];/* Log (base 2) of the number of CQs reserved for firmware use
The reserved resources are numbered from 0 to 2^log2_rsrvd_cqs-1 */
pseudo_bit_treserved7[0x00004];
pseudo_bit_tlog_max_cq_sz[0x00008];/* Log2 of the Maximum CQEs allowed in a CQ */
pseudo_bit_treserved8[0x00008];
/* -------------- */
pseudo_bit_tlog_max_eq[0x00003];/* Log2 of the Maximum number of EQs */
pseudo_bit_treserved9[0x00005];
pseudo_bit_tnum_rsvd_eqs[0x00004];/* The number of EQs reserved for firmware use
The reserved resources are numbered from 0 to num_rsvd_eqs-1
If 0 - no resources are reserved. */
pseudo_bit_treserved10[0x00004];
pseudo_bit_tlog_max_mpts[0x00006];/* Log (base 2) of the maximum number of MPT entries (the number of Regions/Windows) */
pseudo_bit_treserved11[0x00002];
pseudo_bit_tlog_max_eq_sz[0x00008];/* Log2 of the Maximum EQEs allowed in a EQ */
/* -------------- */
pseudo_bit_tlog_max_mtts[0x00006];/* Log2 of the Maximum number of MTT entries */
pseudo_bit_treserved12[0x00002];
pseudo_bit_tlog2_rsvd_mrws[0x00004];/* Log (base 2) of the number of MPTs reserved for firmware use
The reserved resources are numbered from 0 to 2^log2_rsvd_mrws-1 */
pseudo_bit_treserved13[0x00004];
pseudo_bit_tlog_max_mrw_sz[0x00008];/* Log2 of the Maximum Size of Memory Region/Window */
pseudo_bit_treserved14[0x00004];
pseudo_bit_tlog2_rsvd_mtts[0x00004];/* Log (base 2) of the number of MTT entries reserved for firmware use
The reserved resources are numbered from 0 to 2^log2_rsvd_mtts-1
*/
/* -------------- */
pseudo_bit_treserved15[0x00020];
/* -------------- */
pseudo_bit_tlog_max_ra_res_qp[0x00006];/* Log2 of the Maximum number of outstanding RDMA read/Atomic per QP as a responder */
pseudo_bit_treserved16[0x0000a];
pseudo_bit_tlog_max_ra_req_qp[0x00006];/* Log2 of the maximum number of outstanding RDMA read/Atomic per QP as a requester */
pseudo_bit_treserved17[0x0000a];
/* -------------- */
pseudo_bit_tlog_max_ra_res_global[0x00006];/* Log2 of the maximum number of RDMA read/atomic operations the HCA responder can support globally. That implies the RDB table size. */
pseudo_bit_treserved18[0x00016];
pseudo_bit_tlog2_rsvd_rdbs[0x00004];/* Log (base 2) of the number of RDB entries reserved for firmware use
The reserved resources are numbered from 0 to 2^log2_rsvd_rdbs-1 */
/* -------------- */
pseudo_bit_trsz_srq[0x00001];/* Ability to modify the maximum number of WRs per SRQ. */
pseudo_bit_treserved19[0x0001f];
/* -------------- */
pseudo_bit_tnum_ports[0x00004];/* Number of IB ports. */
pseudo_bit_tmax_vl[0x00004];/* Maximum VLs supported on each port, excluding VL15 */
pseudo_bit_tmax_port_width[0x00004];/* IB Port Width
1 - 1x
3 - 1x, 4x
11 - 1x, 4x or 12x
else - Reserved */
pseudo_bit_tmax_mtu[0x00004];/* Maximum MTU Supported
0x0 - Reserved
0x1 - 256
0x2 - 512
0x3 - 1024
0x4 - 2048
0x5 - 0xF Reserved */
pseudo_bit_tlocal_ca_ack_delay[0x00005];/* The Local CA ACK Delay. This is the value recommended to be returned in Query HCA verb.
The delay value in microseconds is computed using 4.096us * 2^(local_ca_ack_delay). */
pseudo_bit_treserved20[0x0000b];
/* -------------- */
pseudo_bit_tlog_max_gid[0x00004];/* Log2 of the maximum number of GIDs per port */
pseudo_bit_treserved21[0x0001c];
/* -------------- */
pseudo_bit_tlog_max_pkey[0x00004];/* Log2 of the max PKey Table Size (per IB port) */
pseudo_bit_treserved22[0x0000c];
pseudo_bit_tstat_rate_support[0x00010];/* bit mask of stat rate supported
bit 0 - full bw
bit 1 - 1/4 bw
bit 2 - 1/8 bw
bit 3 - 1/2 bw; */
/* -------------- */
pseudo_bit_treserved23[0x00020];
/* -------------- */
pseudo_bit_trc[0x00001];/* RC Transport supported */
pseudo_bit_tuc[0x00001];/* UC Transport Supported */
pseudo_bit_tud[0x00001];/* UD Transport Supported */
pseudo_bit_trd[0x00001];/* RD Transport Supported */
pseudo_bit_traw_ipv6[0x00001];/* Raw IPv6 Transport Supported */
pseudo_bit_traw_ether[0x00001];/* Raw Ethertype Transport Supported */
pseudo_bit_tsrq[0x00001];/* SRQ is supported
*/
pseudo_bit_tipo_ib_checksum[0x00001];/* IP over IB checksum is supported */
pseudo_bit_tfw_rev_major[0x00010];/* Firmware Revision - Major */
pseudo_bit_tfw_pages[0x00010];/* Amount of physical memory to be allocated for FW usage is in 4KByte pages. */
/* -------------- */
pseudo_bit_tfw_rev_minor[0x00010];/* Firmware Revision - Minor */
pseudo_bit_tfw_rev_subminor[0x00010];/* Firmware Sub-minor version (Patch level). */
/* -------------- */
pseudo_bit_tcmd_interface_rev[0x00010];/* Command Interface Interpreter Revision ID */
pseudo_bit_treserved0[0x0000e];
pseudo_bit_twqe_h_mode[0x00001];/* Hermon mode. If '1', then WQE and AV format is the advanced format */
pseudo_bit_tzb_wq_cq[0x00001];/* If '1', then ZB mode of WQ and CQ are enabled (i.e. real Memfree PRM is supported) */
/* -------------- */
pseudo_bit_tlog_max_outstanding_cmd[0x00008];/* Log2 of the maximum number of commands the HCR can support simultaneously */
pseudo_bit_treserved1[0x00017];
pseudo_bit_tdt[0x00001];/* Debug Trace Support
0 - Debug trace is not supported
1 - Debug trace is supported */
/* -------------- */
pseudo_bit_tcmd_interface_db[0x00001];/* Set if the device accepts commands by means of special doorbells */
pseudo_bit_treserved2[0x0001f];
/* -------------- */
pseudo_bit_treserved3[0x00060];
/* -------------- */
pseudo_bit_tclr_int_base_addr_h[0x00020];/* Bits [63:32] of Clear interrupt register physical address.
Points to 64 bit register. */
/* -------------- */
pseudo_bit_tclr_int_base_addr_l[0x00020];/* Bits [31:0] of Clear interrupt register physical address.
Points to 64 bit register. */
/* -------------- */
pseudo_bit_treserved4[0x00040];
/* -------------- */
pseudo_bit_terror_buf_start_h[0x00020];/* Read Only buffer for catastrophic error reports (physical address) */
/* -------------- */
pseudo_bit_terror_buf_start_l[0x00020];/* Read Only buffer for catastrophic error reports (physical address) */
/* -------------- */
pseudo_bit_terror_buf_size[0x00020];/* Size in words */
/* -------------- */
pseudo_bit_treserved5[0x00020];
/* -------------- */
pseudo_bit_teq_arm_base_addr_h[0x00020];/* Bits [63:32] of EQ Arm DBs physical address.
Points to 64 bit register.
Setting bit x in the offset, arms EQ number x.
*/
/* -------------- */
pseudo_bit_teq_arm_base_addr_l[0x00020];/* Bits [31:0] of EQ Arm DBs physical address.
Points to 64 bit register.
Setting bit x in the offset, arms EQ number x. */
/* -------------- */
pseudo_bit_teq_set_ci_base_addr_h[0x00020];/* Bits [63:32] of EQ Set CI DBs Table physical address.
Points to a the EQ Set CI DBs Table base address. */
/* -------------- */
pseudo_bit_teq_set_ci_base_addr_l[0x00020];/* Bits [31:0] of EQ Set CI DBs Table physical address.
Points to a the EQ Set CI DBs Table base address. */
/* -------------- */
pseudo_bit_tcmd_db_dw1[0x00010];/* offset in bytes from cmd_db_addr_base where DWord 1 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
pseudo_bit_tcmd_db_dw0[0x00010];/* offset in bytes from cmd_db_addr_base where DWord 0 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
/* -------------- */
pseudo_bit_tcmd_db_dw3[0x00010];/* offset in bytes from cmd_db_addr_base where DWord 3 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
pseudo_bit_tcmd_db_dw2[0x00010];/* offset in bytes from cmd_db_addr_base where DWord 2 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
/* -------------- */
pseudo_bit_tcmd_db_dw5[0x00010];/* offset in bytes from cmd_db_addr_base where DWord 5 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
pseudo_bit_tcmd_db_dw4[0x00010];/* offset in bytes from cmd_db_addr_base where DWord 4 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
/* -------------- */
pseudo_bit_tcmd_db_dw7[0x00010];/* offset in bytes from cmd_db_addr_base where DWord 7 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
pseudo_bit_tcmd_db_dw6[0x00010];/* offset in bytes from cmd_db_addr_base where DWord 6 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
/* -------------- */
pseudo_bit_tcmd_db_addr_base_h[0x00020];/* High bits of cmd_db_addr_base, which cmd_db_dw offsets refer to. Valid only if CmdInterfaceDb bit is '1' */
/* -------------- */
pseudo_bit_tcmd_db_addr_base_l[0x00020];/* Low bits of cmd_db_addr_base, which cmd_db_dw offsets refer to. Valid only if CmdInterfaceDb bit is '1' */
pseudo_bit_ttime_stamp_granularity[0x00008];/* This field controls the granularity in which CQE Timestamp counter is incremented.
The TimeStampGranularity units is 1/4 of a microseconds. (e.g is TimeStampGranularity is configured to 0x2, CQE Timestamp will be incremented every one microsecond)
When sets to Zero, timestamp reporting in the CQE is disabled.
This feature is currently not supported.
*/
pseudo_bit_thca_core_clock[0x00008];/* Internal Clock Period (in units of 1/16 ns) (QUERY_HCA only) */
/* -------------- */
pseudo_bit_treserved2[0x00008];
pseudo_bit_trouter_qp[0x00010];/* Upper 16 bit to be used as a QP number for router mode. Low order 8 bits are taken from the TClass field of the incoming packet.
Valid only if RE bit is set */
pseudo_bit_treserved3[0x00007];
pseudo_bit_tre[0x00001];/* Router Mode Enable
If this bit is set, entire packet (including all headers and ICRC) will be considered as a data payload and will be scattered to memory as specified in the descriptor that is posted on the QP matching the TClass field of packet. */
/* -------------- */
pseudo_bit_tudp[0x00001];/* UD Port Check Enable
0 - Port field in Address Vector is ignored
1 - HCA will check the port field in AV entry (fetched for UD descriptor) against the Port of the UD QP executing the descriptor. */
pseudo_bit_the[0x00001];/* Host Endianess - Used for Atomic Operations
0 - Host is Little Endian
1 - Host is Big endian
*/
pseudo_bit_treserved4[0x00001];
pseudo_bit_tce[0x00001];/* Checksum Enabled - when Set IPoverIB checksum generation & checking is enabled */
pseudo_bit_tsph[0x00001];/* 0 - SW calculates TCP/UDP Pseudo-Header checksum and inserts it into the TCP/UDP checksum field when sending a packet
1 - HW calculates TCP/UDP Pseudo-Header checksum when sending a packet
*/
pseudo_bit_trph[0x00001];/* 0 - Not HW calculation of TCP/UDP Pseudo-Header checksum are done when receiving a packet
1 - HW calculates TCP/UDP Pseudo-Header checksum when receiving a packet
*/
pseudo_bit_treserved5[0x00002];
pseudo_bit_tresponder_exu[0x00004];/* Indicate the relation between the execution enegines allocation dedicated for responder versus the engines dedicated for reqvester .
responder_exu/16 = (number of responder exu engines)/(total number of engines)
Legal values are 0x0-0xF. 0 is "auto".
*/
pseudo_bit_treserved6[0x00004];
pseudo_bit_twqe_quota[0x0000f];/* Maximum number of WQEs that are executed prior to preemption of execution unit. 0 - reserved. */
pseudo_bit_twqe_quota_en[0x00001];/* If set - wqe_quota field is used. If cleared - WQE quota is set to "auto" value */
pseudo_bit_tst[0x00004];/* Event delivery state machine
0x9 - Armed
0xA - Fired
0xB - Always_Armed (auto-rearm)
other - reserved */
pseudo_bit_treserved1[0x00005];
pseudo_bit_toi[0x00001];/* Oerrun ignore.
If set, HW will not check EQ full condition when writing new EQEs. */
pseudo_bit_ttr[0x00001];/* Translation Required. If set - EQ access undergo address translation. */
pseudo_bit_treserved2[0x00005];
pseudo_bit_towner[0x00004];/* 0 - SW ownership
1 - HW ownership
Valid for the QUERY_EQ and HW2SW_EQ commands only */
pseudo_bit_tstatus[0x00004];/* EQ status:
0000 - OK
1010 - EQ write failure
Valid for the QUERY_EQ and HW2SW_EQ commands only */
/* -------------- */
pseudo_bit_tstart_address_h[0x00020];/* Start Address of Event Queue[63:32]. */
/* -------------- */
pseudo_bit_tstart_address_l[0x00020];/* Start Address of Event Queue[31:0].
Must be aligned on 32-byte boundary */
/* -------------- */
pseudo_bit_treserved3[0x00018];
pseudo_bit_tlog_eq_size[0x00005];/* Amount of entries in this EQ is 2^log_eq_size.
Log_eq_size must be bigger than 1.
Maximum EQ size is 2^17 EQEs (max Log_eq_size is 17). */
pseudo_bit_treserved4[0x00003];
/* -------------- */
pseudo_bit_treserved5[0x00020];
/* -------------- */
pseudo_bit_tintr[0x00008];/* Interrupt (message) to be generated to report event to INT layer.
00iiiiii - set to INTA given in QUERY_ADAPTER in order to generate INTA messages on Express.
10jjjjjj - specificies type of interrupt message to be generated (total 64 different messages supported).
All other values are reserved and should not be used.
If interrupt generation is not required, ST field must be set upon creation to Fired state. No EQ arming doorbell should be performed. In this case hardware will not generate any interrupt. */
pseudo_bit_treserved6[0x00018];
/* -------------- */
pseudo_bit_tpd[0x00018];/* PD to be used to access EQ */
pseudo_bit_treserved7[0x00008];
/* -------------- */
pseudo_bit_tlkey[0x00020];/* Memory key (L-Key) to be used to access EQ */
/* -------------- */
pseudo_bit_treserved8[0x00040];
/* -------------- */
pseudo_bit_tconsumer_indx[0x00020];/* Contains next entry to be read upon polling the event queue.
Must be initalized to zero while opening EQ */
/* -------------- */
pseudo_bit_tproducer_indx[0x00020];/* Contains next entry in EQ to be written by the HCA.
pseudo_bit_tptag_h[0x00020];/* High-order bits of physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */
/* -------------- */
pseudo_bit_tp[0x00001];/* Present bit. If set, page entry is valid. If cleared, access to this page will generate non-present page access fault. */
pseudo_bit_treserved0[0x0000b];
pseudo_bit_tptag_l[0x00014];/* Low-order bits of Physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */
pseudo_bit_tlkey[0x00020];/* Must be 0 for SW2HW_MPT.
On QUERY_MPT and HW2SW_MPT commands for Memory Window it reflects the LKey of the Region that the Window is bound to.
The field holds the lkey field in the following semantics: {key[7:0],key[31:8]}. */
/* -------------- */
pseudo_bit_twin_cnt[0x00020];/* Number of windows bound to this region. Valid for regions only.
The field is valid only for the QUERY_MPT and HW2SW_MPT commands. */
/* -------------- */
pseudo_bit_treserved5[0x00020];
/* -------------- */
pseudo_bit_tmtt_adr_h[0x00006];/* Base (first) address of the MTT relative to MTT base in the ICM */
pseudo_bit_treserved6[0x0001a];
/* -------------- */
pseudo_bit_treserved7[0x00003];
pseudo_bit_tmtt_adr_l[0x0001d];/* Base (first) address of the MTT relative to MTT base address in the ICM. Must be aligned on 8 bytes. */
/* -------------- */
pseudo_bit_tmtt_sz[0x00020];/* Number of MTT entries allocated for this MR.
When Fast Registration Operations can not be executed on this region (FRE bit is zero) this field is reserved.
When Fast Registration Operation is enabled (FRE bit is set) this field indicates the number of MTTs allocated for this MR. If mtt_sz value is zero, there is no limit for the numbers of MTTs and the HCA does not check this field when executing fast register WQE. */
Valid for the QUERY_CQ and HW2SW_CQ commands only. */
pseudo_bit_treserved1[0x00005];
pseudo_bit_toi[0x00001];/* When set, overrun ignore is enabled.
When set, Updates of CQ consumer counter (poll for completion) or Request completion notifications (Arm CQ) doorbells should not be rang on that CQ. */
pseudo_bit_treserved2[0x0000a];
pseudo_bit_tstatus[0x00004];/* CQ status
0000 - OK
1001 - CQ overflow
1010 - CQ write failure
Valid for the QUERY_CQ and HW2SW_CQ commands only */
/* -------------- */
pseudo_bit_tstart_address_h[0x00020];/* Start address of CQ[63:32].
Must be aligned on CQE size (32 bytes) */
/* -------------- */
pseudo_bit_tstart_address_l[0x00020];/* Start address of CQ[31:0].
Must be aligned on CQE size (32 bytes) */
/* -------------- */
pseudo_bit_tusr_page[0x00018];/* UAR page this CQ can be accessed through (ringinig CQ doorbells) */
pseudo_bit_tlog_cq_size[0x00005];/* Log (base 2) of the CQ size (in entries).
Maximum CQ size is 2^17 CQEs (max log_cq_size is 17) */
pseudo_bit_treserved3[0x00003];
/* -------------- */
pseudo_bit_treserved4[0x00020];
/* -------------- */
pseudo_bit_tc_eqn[0x00008];/* Event Queue this CQ reports completion events to.
Valid values are 0 to 63
If configured to value other than 0-63, completion events will not be reported on the CQ. */
pseudo_bit_treserved5[0x00018];
/* -------------- */
pseudo_bit_tpd[0x00018];/* Protection Domain to be used to access CQ.
Must be the same PD of the CQ L_Key. */
pseudo_bit_treserved6[0x00008];
/* -------------- */
pseudo_bit_tl_key[0x00020];/* Memory key (L_Key) to be used to access CQ */
/* -------------- */
pseudo_bit_tlast_notified_indx[0x00020];/* Maintained by HW.
Valid for QUERY_CQ and HW2SW_CQ commands only. */
/* -------------- */
pseudo_bit_tsolicit_producer_indx[0x00020];/* Maintained by HW.
Valid for QUERY_CQ and HW2SW_CQ commands only.
*/
/* -------------- */
pseudo_bit_tconsumer_counter[0x00020];/* Consumer counter is a 32bits counter that is incremented for each CQE pooled from the CQ.
Must be 0x0 in CQ initialization.
Valid for the QUERY_CQ and HW2SW_CQ commands only. */
/* -------------- */
pseudo_bit_tproducer_counter[0x00020];/* Producer counter is a 32bits counter that is incremented for each CQE that is written by the HW to the CQ.
CQ overrun is reported if Producer_counter + 1 equals to Consumer_counter and a CQE needs to be added..
Maintained by HW (valid for the QUERY_CQ and HW2SW_CQ commands only) */
/* -------------- */
pseudo_bit_tcqn[0x00018];/* CQ number. Least significant bits are constrained by the position of this CQ in CQC table
Valid for the QUERY_CQ and HW2SW_CQ commands only */
pseudo_bit_treserved7[0x00008];
/* -------------- */
pseudo_bit_tcq_ci_db_record[0x00020];/* Index in the UAR Context Table Entry.
HW uses this index as an offset from the UAR Context Table Entry in order to read this CQ Consumer Counter doorbell record.
This value can be retrieved from the HW in the QUERY_CQ command. */
/* -------------- */
pseudo_bit_tcq_state_db_record[0x00020];/* Index in the UAR Context Table Entry.
HW uses this index as an offset from the UAR Context Table Entry in order to read this CQ state doorbell record.
This value can be retrieved from the HW in the QUERY_CQ command. */
pseudo_bit_tstatus[0x00010];/* PCI Status Register */
/* -------------- */
pseudo_bit_trevision_id[0x00008];
pseudo_bit_tclass_code_hca_class_code[0x00018];
/* -------------- */
pseudo_bit_tcache_line_size[0x00008];/* Cache Line Size */
pseudo_bit_tlatency_timer[0x00008];
pseudo_bit_theader_type[0x00008];/* hardwired to zero */
pseudo_bit_tbist[0x00008];
/* -------------- */
pseudo_bit_tbar0_ctrl[0x00004];/* hard-wired to 0100 */
pseudo_bit_treserved0[0x00010];
pseudo_bit_tbar0_l[0x0000c];/* Lower bits of BAR0 (Device Configuration Space) */
/* -------------- */
pseudo_bit_tbar0_h[0x00020];/* Upper 32 bits of BAR0 (Device Configuration Space) */
/* -------------- */
pseudo_bit_tbar1_ctrl[0x00004];/* Hardwired to 1100 */
pseudo_bit_treserved1[0x00010];
pseudo_bit_tbar1_l[0x0000c];/* Lower bits of BAR1 (User Access Region - UAR - space) */
/* -------------- */
pseudo_bit_tbar1_h[0x00020];/* upper 32 bits of BAR1 (User Access Region - UAR - space) */
/* -------------- */
pseudo_bit_tbar2_ctrl[0x00004];/* Hardwired to 1100 */
pseudo_bit_treserved2[0x00010];
pseudo_bit_tbar2_l[0x0000c];/* Lower bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */
/* -------------- */
pseudo_bit_tbar2_h[0x00020];/* Upper 32 bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */
/* -------------- */
pseudo_bit_tcardbus_cis_pointer[0x00020];
/* -------------- */
pseudo_bit_tsubsystem_vendor_id[0x00010];/* Specified by the device NVMEM configuration */
pseudo_bit_tsubsystem_id[0x00010];/* Specified by the device NVMEM configuration */
/* -------------- */
pseudo_bit_texpansion_rom_enable[0x00001];/* Expansion ROM Enable. Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */
pseudo_bit_treserved3[0x0000a];
pseudo_bit_texpansion_rom_base_address[0x00015];/* Expansion ROM Base Address (upper 21 bit). Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */
/* -------------- */
pseudo_bit_tcapabilities_pointer[0x00008];/* Specified by the device NVMEM configuration */
pseudo_bit_treserved4[0x00018];
/* -------------- */
pseudo_bit_treserved5[0x00020];
/* -------------- */
pseudo_bit_tinterrupt_line[0x00008];
pseudo_bit_tinterrupt_pin[0x00008];
pseudo_bit_tmin_gnt[0x00008];
pseudo_bit_tmax_latency[0x00008];
/* -------------- */
pseudo_bit_treserved6[0x00100];
/* -------------- */
pseudo_bit_tmsi_cap_id[0x00008];
pseudo_bit_tmsi_next_cap_ptr[0x00008];
pseudo_bit_tmsi_en[0x00001];
pseudo_bit_tmultiple_msg_cap[0x00003];
pseudo_bit_tmultiple_msg_en[0x00003];
pseudo_bit_tcap_64_bit_addr[0x00001];
pseudo_bit_treserved7[0x00008];
/* -------------- */
pseudo_bit_tmsg_addr_l[0x00020];
/* -------------- */
pseudo_bit_tmsg_addr_h[0x00020];
/* -------------- */
pseudo_bit_tmsg_data[0x00010];
pseudo_bit_treserved8[0x00010];
/* -------------- */
pseudo_bit_treserved9[0x00080];
/* -------------- */
pseudo_bit_tpm_cap_id[0x00008];/* Power management capability ID - 01h */
pseudo_bit_tpm_next_cap_ptr[0x00008];
pseudo_bit_tpm_cap[0x00010];/* [2:0] Version - 02h
[3] PME clock - 0h
[4] RsvP
[5] Device specific initialization - 0h
[8:6] AUX current - 0h
[9] D1 support - 0h
[10] D2 support - 0h
[15:11] PME support - 0h */
/* -------------- */
pseudo_bit_tpm_status_control[0x00010];/* [14:13] - Data scale - 0h */
pseudo_bit_tpm_control_status_brdg_ext[0x00008];
pseudo_bit_tdata[0x00008];
/* -------------- */
pseudo_bit_treserved10[0x00040];
/* -------------- */
pseudo_bit_tvpd_cap_id[0x00008];/* 03h */
pseudo_bit_tvpd_next_cap_id[0x00008];
pseudo_bit_tvpd_address[0x0000f];
pseudo_bit_tf[0x00001];
/* -------------- */
pseudo_bit_tvpd_data[0x00020];
/* -------------- */
pseudo_bit_treserved11[0x00040];
/* -------------- */
pseudo_bit_tpciex_cap_id[0x00008];/* PCI-Express capability ID - 10h */
pseudo_bit_tpciex_next_cap_ptr[0x00008];
pseudo_bit_tpciex_cap[0x00010];/* [3:0] Capability version - 1h
structarbelprm_page_fault_event_data_st{/* Little Endian */
pseudo_bit_tva_h[0x00020];/* Virtual Address[63:32] this page fault is reported on */
/* -------------- */
pseudo_bit_tva_l[0x00020];/* Virtual Address[63:32] this page fault is reported on */
/* -------------- */
pseudo_bit_tmem_key[0x00020];/* Memory Key this page fault is reported on */
/* -------------- */
pseudo_bit_tqp[0x00018];/* QP this page fault is reported on */
pseudo_bit_treserved0[0x00003];
pseudo_bit_ta[0x00001];/* If set the memory access that caused the page fault was atomic */
pseudo_bit_tlw[0x00001];/* If set the memory access that caused the page fault was local write */
pseudo_bit_tlr[0x00001];/* If set the memory access that caused the page fault was local read */
pseudo_bit_trw[0x00001];/* If set the memory access that caused the page fault was remote write */
pseudo_bit_trr[0x00001];/* If set the memory access that caused the page fault was remote read */
/* -------------- */
pseudo_bit_tpd[0x00018];/* PD this page fault is reported on */
pseudo_bit_treserved1[0x00008];
/* -------------- */
pseudo_bit_tprefetch_len[0x00020];/* Indicates how many subsequent pages in the same memory region/window will be accessed by the following transaction after this page fault is resolved. measured in bytes. SW can use this information in order to page-in the subsequent pages if they are not present. */
structarbelprm_qp_ee_state_transitions_st{/* Little Endian */
pseudo_bit_topt_param_mask[0x00020];/* This field defines which optional parameters are passed. Each bit specifies whether optional parameter is passed (set) or not (cleared). The optparammask is defined for each QP/EE command. */
/* -------------- */
pseudo_bit_treserved0[0x00020];
/* -------------- */
structarbelprm_queue_pair_ee_context_entry_stqpc_eec_data;/* QPC/EEC data */
structarbelprm_completion_queue_entry_st{/* Little Endian */
pseudo_bit_tmy_qpn[0x00018];/* Indicates the QP for which completion is being reported */
pseudo_bit_treserved0[0x00004];
pseudo_bit_tver[0x00004];/* CQE version.
0 for InfiniHost-III-EX */
/* -------------- */
pseudo_bit_tmy_ee[0x00018];/* EE context (for RD only).
Invalid for Bind and Nop operation on RD.
For non RD services this filed reports the CQE timestamp. The Timestamp is a free running counter that is incremented every TimeStampGranularity tick. The counter rolls-over when it reaches saturation. TimeStampGranularity is configured in the INIT_HCA command. This feature is currently not supported.
*/
pseudo_bit_tchecksum_15_8[0x00008];/* Checksum[15:8] - See IPoverIB checksum offloading chapter */
/* -------------- */
pseudo_bit_trqpn[0x00018];/* Remote (source) QP number. Valid in Responder CQE only for Datagram QP. */
pseudo_bit_tchecksum_7_0[0x00008];/* Checksum[7:0] - See IPoverIB checksum offloading chapter */
/* -------------- */
pseudo_bit_trlid[0x00010];/* Remote (source) LID of the message. Valid in Responder of UD QP CQE only. */
pseudo_bit_tml_path[0x00007];/* My (destination) LID path bits - these are the lowemost LMC bits of the DLID in an incoming UD packet, higher bits of this field, that are not part of the LMC bits are zeroed by HW.
Valid in responder of UD QP CQE only.
Invalid if incoming message DLID is the permissive LID or incoming message is multicast. */
pseudo_bit_tg[0x00001];/* GRH present indicator. Valid in Responder of UD QP CQE only. */
pseudo_bit_tipok[0x00001];/* IP OK - See IPoverIB checksum offloading chapter */
pseudo_bit_treserved1[0x00003];
pseudo_bit_tsl[0x00004];/* Service Level of the message. Valid in Responder of UD QP CQE only. */
/* -------------- */
pseudo_bit_timmediate_ethertype_pkey_indx_eecredits[0x00020];/* Valid for receive queue completion only.
If Opcode field indicates that this was send/write with immediate, this field contains immediate field of the packet.
If completion corresponds to RAW receive queue, bits 15:0 contain Ethertype field of the packet.
If completion corresponds to GSI receive queue, bits 31:16 contain index in PKey table that matches PKey of the message arrived.
If Opcode field indicates that this was send and invalidate, this field contains the key that was invalidated.
For CQE of send queue of the reliable connection service (but send and invalide), bits [4:0] of this field contain the encoded EEcredits received in last ACK of the message. */
/* -------------- */
pseudo_bit_tbyte_cnt[0x00020];/* Byte count of data actually transferred (valid for receive queue completions only) */
/* -------------- */
pseudo_bit_treserved2[0x00006];
pseudo_bit_twqe_adr[0x0001a];/* Bits 31:6 of WQE virtual address completion is reported for. The 6 least significant bits are zero. */
/* -------------- */
pseudo_bit_treserved3[0x00007];
pseudo_bit_towner[0x00001];/* Owner field. Zero value of this field means SW ownership of CQE. */
pseudo_bit_treserved4[0x0000f];
pseudo_bit_ts[0x00001];/* If set, completion is reported for Send queue, if cleared - receive queue. */
pseudo_bit_topcode[0x00008];/* The opcode of WQE completion is reported for.
For CQEs corresponding to send completion, NOPCODE field of the WQE is copied to this field.
For CQEs corresponding to receive completions, opcode field of last packet in the message copied to this field.
For CQEs corresponding to the receive queue of QPs mapped to QP1, the opcode will be SEND with Immediate (messages are guaranteed to be SEND only)
The following values are reported in case of completion with error:
0xFE - For completion with error on Receive Queues
0xFF - For completion with error on Send Queues */
pseudo_bit_terr_ba[0x00002];/* Error bank address */
pseudo_bit_treserved3[0x00011];
pseudo_bit_toverflow[0x00001];/* Fatal: ECC error FIFO overflow - ECC errors were detected, which may or may not have been corrected by InfiniHost-III-EX */
